Rakesh Kumar
Orcid: 0009-0008-1535-1889Affiliations:
- University of Illinois at Urbana-Champaign, IL, USA
- University of California, San Diego, USA (PhD 2006)
According to our database1,
Rakesh Kumar
authored at least 108 papers
between 2002 and 2023.
Collaborative distances:
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Bibliography
2023
Understanding Interactions Between Chip Architecture and Uncertainties in Semiconductor Supply and Demand.
CoRR, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Exploiting Short Application Lifetimes for Low Cost Hardware Encryption in Flexible Electronics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
FlexiCores: low footprint, high yield, field reprogrammable flexible microprocessors.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
2021
When Tiny Goes Big: A Computer Architect's View of the Emerging Internet of Tiny Things.
GetMobile Mob. Comput. Commun., 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Proceedings of the 2019 Winter Simulation Conference, 2019
Proceedings of the 2019 Workshop on Hot Topics in Video Analytics and Intelligent Edges, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
ACM Trans. Model. Comput. Simul., 2018
IEEE Micro, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the 2018 IEEE 26th International Conference on Network Protocols, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors.
ACM Trans. Comput. Syst., 2017
Melody: Synthesized datasets for evaluating intrusion detection systems for the smart grid.
Proceedings of the 2017 Winter Simulation Conference, 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
Proceedings of the 2016 IEEE International Conference on Smart Grid Communications, 2016
Proceedings of the 2016 annual ACM Conference on SIGSIM Principles of Advanced Discrete Simulation, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Parity Helix: Efficient protection for single-dimensional faults in multi-dimensional memory systems.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
it Inf. Technol., 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
2014
J. Comput. Sci. Technol., 2014
ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems.
Proceedings of the International Conference for High Performance Computing, 2014
Software canaries: software-based path delay fault testing for variation-aware energy-efficient design.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Branch and Data Herding: Reducing Control and Memory Divergence for Error-Tolerant GPU Applications.
IEEE Trans. Multim., 2013
ACM Trans. Embed. Comput. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity.
IEEE Comput. Archit. Lett., 2013
Proceedings of the International Conference for High Performance Computing, 2013
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013
Statistical analysis and modeling for error composition in approximate computation circuits.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
An algorithmic approach to error localization and partial recomputation for low-overhead fault tolerance.
Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Stochastic computing: embracing errors in architectureand design of processors and applications.
Proceedings of the 14th International Conference on Compilers, 2011
Proceedings of the 14th International Conference on Compilers, 2011
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
Int. J. Reconfigurable Comput., 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Recovery-driven design: a power minimization methodology for error-tolerant processor modules.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08).
SIGARCH Comput. Archit. News, 2009
Workload adaptive shared memory multicore processors with reconfigurable interconnects.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Three scalable approaches to improving many-core throughput for a given peak power budget.
Proceedings of the 16th International Conference on High Performance Computing, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 2009 International Conference on Compilers, 2009
2008
SIGARCH Comput. Archit. News, 2008
Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07).
SIGARCH Comput. Archit. News, 2008
2007
Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06).
SIGARCH Comput. Archit. News, 2007
Adv. Comput., 2007
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007
2006
Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006
2005
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05).
SIGARCH Comput. Archit. News, 2005
IEEE Comput. Archit. Lett., 2005
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
2004
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004
2003
IEEE Comput. Archit. Lett., 2003
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
2002
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Software Energy Optimization of Real Time Preemptive Tasks by Minimizing Cache-Related Preemption Costs.
Proceedings of the High Performance Computing, 4th International Symposium, 2002