Isidoros Sideris

According to our database1, Isidoros Sideris authored at least 18 papers between 2005 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
A column parity based fault detection mechanism for FIFO buffers.
Integr., 2013

An analytical framework for estimating TCO and exploring data center design space.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2012
Cost Effective Protection Techniques for TCAM Memory Arrays.
IEEE Trans. Computers, 2012

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2011
Eliminating energy of same-content-cell-columns of on-chip SRAM arrays.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010
A hardware peripheral for Java bytecodes translation acceleration.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

A fast multiplier-less edge detection accelerator for FPGAs.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

2009
Extending an embedded RISC microprocessor for efficient translation based Java execution.
Microprocess. Microsystems, 2009

2008
A predecoding technique for ILP exploitation in Java processors.
J. Syst. Archit., 2008

An instruction set extension for java bytecodes translation acceleration.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

A BISR Architecture for Embedded Memories.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability.
Proceedings of the 2008 16th European Signal Processing Conference, 2008

2007
Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Building embedded DSP applications in a Java modeling framework.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
A cache based stack folding technique for high performance Java processors.
Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems, 2006

Segmentation based design of serial parallel multipliers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Methodology for Design Space Exploration in Embedded DSP Applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Novel systolic schemes for serial-parallel multiplication.
Proceedings of the 13th European Signal Processing Conference, 2005


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