Kiamal Z. Pekmestzi

According to our database, Kiamal Z. Pekmestzi authored at least 99 papers between 1996 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Approximate Computing Survey, Part II: Application-Specific & Architectural Approximation Techniques and Applications.

Vasileios Leon, Muhammad Abdullah Hanif, Giorgos Armeniakos, Xun Jiao, Muhammad Shafique, Kiamal Z. Pekmestzi, Dimitrios Soudris

CoRR, 2023

Approximate Computing Survey, Part I: Terminology and Software & Hardware Approximation Techniques.

Vasileios Leon, Muhammad Abdullah Hanif, Giorgos Armeniakos, Xun Jiao, Muhammad Shafique, Kiamal Z. Pekmestzi, Dimitrios Soudris

CoRR, 2023

2022

Systematic Embedded Development and Implementation Techniques on Intel Myriad VPUs.

Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators.

Vasileios Leon, Georgios Makris, Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2021

Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers.

Vasileios Leon, Theodora Paparouni, Evangelos Petrongonas, Dimitrios Soudris, Kiamal Z. Pekmestzi

ACM Trans. Embed. Comput. Syst., 2021

Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators.

Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020

On the Diminished-1 Modulo 2n+1 Addition and Subtraction.

Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos

J. Circuits Syst. Comput., 2020

Efficient design of magnitude and 2's complement comparators.

Fotios Ntouskas, Constantinos Efstathiou, Kiamal Z. Pekmestzi

Integr., 2020

Combining Arithmetic Approximation Techniques for Improved CNN Circuit Design.

George Lentaris, George Chatzitsompanis, Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints.

Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Energy-efficient VLSI implementation of multipliers with double LSB operands.

Vasileios Leon, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi

IET Circuits Devices Syst., 2019

TF2FPGA: A Framework for Projecting and Accelerating Tensorflow CNNs on FPGA Platforms.

Spyridon Mouselinos, Vasileios Leon, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi

Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers.

Vasileios Leon, Konstantinos Asimakopoulos, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits.

Georgios Zervakis, Fotios Ntouskas, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi

IEEE Trans. Very Large Scale Integr. Syst., 2018

Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers.

Vasileios Leon, Georgios Zervakis, Dimitrios Soudris, Kiamal Z. Pekmestzi

IEEE Trans. Very Large Scale Integr. Syst., 2018

Walking through the Energy-Error Pareto Frontier of Approximate Multipliers.

Vasileios Leon, Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi

IEEE Micro, 2018

Efficient support vector machines implementation on Intel/Movidius Myriad 2.

Charalampos Marantos, Nikolaos Karavalakis, Vasileios Leon, Vasileios Tsoutsouras, Kiamal Z. Pekmestzi, Dimitrios Soudris

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2017

DIRT latch: A novel low cost double node upset tolerant latch.

Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi

Microelectron. Reliab., 2017

On the design of the FFT Butterfly Units.

Fotis Douskas, Kiamal Z. Pekmestzi

Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

2016

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation.

Georgios Zervakis, Kostas Tsoumanis, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi

IEEE Trans. Very Large Scale Integr. Syst., 2016

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic.

Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis, Kiamal Z. Pekmestzi

IEEE Trans. Very Large Scale Integr. Syst., 2016

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding.

Kostas Tsoumanis, Nicholas Axelos, Nikolaos Moschopoulos, Georgios Zervakis, Kiamal Z. Pekmestzi

IEEE Trans. Computers, 2016

Low latency radiation tolerant self-repair reconfigurable SRAM architecture.

Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi

Microelectron. Reliab., 2016

Fused modulo 2n + 1 add-multiply unit for weighted operands.

Kiamal Z. Pekmestzi, Kostas Tsoumanis, Constantinos Efstathiou

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Design of Efficient 1's Complement Modified Booth Multiplier.

Kiamal Z. Pekmestzi, Constantinos Efstathiou

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

Delta DICE: A Double Node Upset resilient latch.

Nikolaos Eftaxiopoulos, Nicholas Axelos, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

DONUT: A Double Node Upset Tolerant Latch.

Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Modulo 2n ± 1 Fused Add-Multiply Units.

Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Hybrid approximate multiplier architectures for improved power-accuracy trade-offs.

Georgios Zervakis, Sotirios Xydis, Kostas Tsoumanis, Dimitrios Soudris, Kiamal Z. Pekmestzi

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Low leakage radiation tolerant CAM/TCAM cell.

Nikolaos Eftaxiopoulos-Sarris, Nicholas Axelos, Kiamal Z. Pekmestzi

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis.

Georgios Zervakis, Kostas Tsoumanis, Sotirios Xydis, Nicholas Axelos, Kiamal Z. Pekmestzi

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator.

Kostas Tsoumanis, Sotirios Xydis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Efficient modulo 2ⁿ+1 multiply and multiply-add units based on modified Booth encoding.

Constantinos Efstathiou, Nikos K. Moshopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi

Integr., 2014

FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs.

Nicholas Axelos, Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A high radix montgomery multiplier with concurrent error detection.

Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi

Proceedings of the 9th International Design and Test Symposium, 2014

Modulo 2ⁿ+1 addition and multiplication for redundant operands.

Kostas Tsoumanis, Constantinos Efstathiou, Kiamal Z. Pekmestzi

Proceedings of the 9th International Design and Test Symposium, 2014

An independent dual gate SOI FinFET soft-error resilient memory cell.

Nikolaos Eftaxiopoulos-Sarris, Nicholas Axelos, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi

Proceedings of the 9th International Design and Test Symposium, 2014

High performance MAC designs.

Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kiamal Z. Pekmestzi, Costas Efstathiou

Proceedings of the 9th International Design and Test Symposium, 2014

Fused modulo 2ⁿ - 1 add-multiply unit.

Kostas Tsoumanis, Kiamal Z. Pekmestzi, Constantinos Efstathiou

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

On the design of efficient modulo 2ⁿ+1 multiply-add-add units.

Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

A segmentation-based BISR scheme.

Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A column parity based fault detection mechanism for FIFO buffers.

Isidoros Sideris, Kiamal Z. Pekmestzi

Integr., 2013

On the design of modulo 2ⁿ + 1 dot product and generalized multiply-add units.

Costas Efstathiou, Nikolaos Moschopoulos, Ioannis Voyiatzis, Kiamal Z. Pekmestzi

Comput. Electr. Eng., 2013

On the design of modulo 2ⁿ±1 residue generators.

Kostas Tsoumanis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A radiation tolerant and self-repair memory cell.

Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Efficient modulo 2ⁿ+1 multiplication for the idea block cipher.

Kiamal Z. Pekmestzi, Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Efficient Memory Repair Using Cache-Based Redundancy.

Nicholas Axelos, Kiamal Z. Pekmestzi, Dimitris Gizopoulos

IEEE Trans. Very Large Scale Integr. Syst., 2012

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs.

Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos

ACM Trans. Design Autom. Electr. Syst., 2012

Cost Effective Protection Techniques for TCAM Memory Arrays.

Isidoros Sideris, Kiamal Z. Pekmestzi

IEEE Trans. Computers, 2012

On the Design of Configurable Modulo 2n±1 Residue Generators.

Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis, Kiamal Z. Pekmestzi

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

High Performance and Area Efficient Flexible DSP Datapath Synthesis.

Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi

IEEE Trans. Very Large Scale Integr. Syst., 2011

On the Design of Modulo 2^n+1 Multipliers.

Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nicholas Axelos

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms.

Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Z. Pekmestzi

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A hardware peripheral for Java bytecodes translation acceleration.

Isidoros Sideris, Nikos K. Moshopoulos, Kiamal Z. Pekmestzi

Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

A fast multiplier-less edge detection accelerator for FPGAs.

Nikos Anastasiadis, Isidoros Sideris, Kiamal Z. Pekmestzi

Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework.

Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching.

Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.

Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures.

Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A New Low-Power Soft-Error Tolerant SRAM Cell.

Nicholas Axelos, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology.

Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A bit level area aware cache-based architecture for memory repairs.

Nicholas Axelos, Kiamal Z. Pekmestzi

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009

Extending an embedded RISC microprocessor for efficient translation based Java execution.

Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos

Microprocess. Microsystems, 2009

Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths.

Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi

Integr., 2009

A design methodology for high-performance and low-leakage fixed-point transpose FIR filters.

Dimitris Bekiaris, Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining.

Sotirios Xydis, Ioannis Triantafyllou, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008

A predecoding technique for ILP exploitation in Java processors.

Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos

J. Syst. Archit., 2008

An instruction set extension for java bytecodes translation acceleration.

Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

A BISR Architecture for Embedded Memories.

Kiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A high-speed radix-4 multiplexer-based array multiplier.

Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability.

Sotirios Xydis, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the 2008 16th European Signal Processing Conference, 2008

Efficient serial and parallel implementation of programmable fir filters based on the merging technique.

Dimitris Bekiaris, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the 2008 16th European Signal Processing Conference, 2008

Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility.

Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007

Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme.

Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding.

Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic.

Dimitris Bekiaris, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the 14th IEEE International Conference on Electronics, 2007

A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware.

Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the 15th European Signal Processing Conference, 2007

Building embedded DSP applications in a Java modeling framework.

Isidoros Sideris, Dimitris Pilitsos, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the 15th European Signal Processing Conference, 2007

A Reconfigurable Arithmetic Data-path Based On Regular Interconnection.

Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006

A cache based stack folding technique for high performance Java processors.

Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi

Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems, 2006

Segmentation based design of serial parallel multipliers.

Paul Bougas, Andreas Tsirikos, Kostas Anagnostopoulos, Isidoros Sideris, Kiamal Z. Pekmestzi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.

Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Large Scale Adaptable Multiplier for Cryptographic Applications.

Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005

A New Low Latency Parallel FIR Filter Scheme.

Paraskevas Kalivas, Vassilis Vassilakis, Chris Meletis, Kiamal Z. Pekmestzi

J. VLSI Signal Process., 2005

Pipelined array-based FIR filter folding.

Paul Bougas, Paraskevas Kalivas, Andreas Tsirikos, Kiamal Z. Pekmestzi

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Novel systolic schemes for serial-parallel multiplication.

Isidoros Sideris, Kostas Anagnostopoulos, Paraskevas Kalivas, Kiamal Z. Pekmestzi

Proceedings of the 13th European Signal Processing Conference, 2005

100% operational efficient bit-serial programmable FIR digital filters.

Paraskevas Kalivas, Andreas Tsirikos, Paul Bougas, Kiamal Z. Pekmestzi

Proceedings of the 13th European Signal Processing Conference, 2005

Long Number Bit-Serial Squarers.

E. Chaniotakis, Paraskevas Kalivas, Kiamal Z. Pekmestzi

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004

Low-latency and high-efficiency bit serial-serial multipliers.

Paraskevas Kalivas, Kiamal Z. Pekmestzi, Paul Bougas, Andreas Tsirikos, Kostas Gotsis

Proceedings of the 2004 12th European Signal Processing Conference, 2004

Pipeline array implementation of FIR filters.

Paraskevas Kalivas, Paul Bougas, Vassilis Vassilakis, Christos Meletis, Kiamal Z. Pekmestzi

Proceedings of the 2004 12th European Signal Processing Conference, 2004

2002

A Systolic, High Speed Architecture for an RSA Cryptosystem.

Kiamal Z. Pekmestzi, Nikos K. Moshopoulos

J. VLSI Signal Process., 2002

2001

A bit-interleaved systolic architecture for a high-speed RSA system.

Kiamal Z. Pekmestzi, Nikos K. Moshopoulos

Integr., 2001

A Novel Systolic Architecture for Efficient RSA Implementation.

Nikos K. Moshopoulos, Kiamal Z. Pekmestzi

Proceedings of the Public Key Cryptography, 2001

On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms.

Kostas Marinis, Nikos K. Moshopoulos, Fotis Karoubalis, Kiamal Z. Pekmestzi

Proceedings of the Information Security, 4th International Conference, 2001

2000

Constant Number Serial Pipeline Multipliers.

Kiamal Z. Pekmestzi, Paraskevas Kalivas

J. VLSI Signal Process., 2000

A systolic serial squarer of continuous operation.

Kiamal Z. Pekmestzi, Nikolaos Moshopoulos, Paraskevas Kalivas

Proceedings of the 10th European Signal Processing Conference, 2000

1998

A scheme for the VLSI implementation of FIR digital filters with reduced latency.

Christos Gr. Caraiscos, Kiamal Z. Pekmestzi

Proceedings of the 9th European Signal Processing Conference, 1998

1997

Hardware compilation using attribute grammars.

George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas

Proceedings of the Advances in Hardware Design and Verification, 1997

1996

Systolic digital filters with reduced latency - serial implementation.

Christos Gr. Caraiscos, Kiamal Z. Pekmestzi

Int. J. Circuit Theory Appl., 1996