Nicholas Axelos

According to our database1, Nicholas Axelos authored at least 17 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
DIRT latch: A novel low cost double node upset tolerant latch.
Microelectron. Reliab., 2017

2016
Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding.
IEEE Trans. Computers, 2016

Low latency radiation tolerant self-repair reconfigurable SRAM architecture.
Microelectron. Reliab., 2016

2015
Delta DICE: A Double Node Upset resilient latch.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

DONUT: A Double Node Upset Tolerant Latch.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Low leakage radiation tolerant CAM/TCAM cell.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Efficient modulo 2<sup>n</sup>+1 multiply and multiply-add units based on modified Booth encoding.
Integr., 2014

FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A high radix montgomery multiplier with concurrent error detection.
Proceedings of the 9th International Design and Test Symposium, 2014

An independent dual gate SOI FinFET soft-error resilient memory cell.
Proceedings of the 9th International Design and Test Symposium, 2014

A segmentation-based BISR scheme.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2012
Efficient Memory Repair Using Cache-Based Redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2011
On the Design of Modulo 2^n+1 Multipliers.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
A New Low-Power Soft-Error Tolerant SRAM Cell.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A bit level area aware cache-based architecture for memory repairs.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2008
A BISR Architecture for Embedded Memories.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008


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