Yiannakis Sazeides

According to our database1, Yiannakis Sazeides authored at least 53 papers between 1996 and 2019.

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Bibliography

2019
Comprehensive Characterization of an Open Source Document Search Engine.
TACO, 2019

GeST: An Automatic Framework For Generating CPU Stress-Tests.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Sensing CPU Voltage Noise Through Electromagnetic Emanations.
Computer Architecture Letters, 2018

Fast Estimations of Failure Probability Over Long Time Spans.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

To Detect or to Correct?
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018


2017
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers.
J. Parallel Distrib. Comput., 2017

A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application.
CoRR, 2017

Error-Resilient Server Ecosystems for Edge and Cloud Datacenters.
IEEE Computer, 2017


2016
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures.
TACO, 2016

Toward Multi-Layer Holistic Evaluation of System Designs.
Computer Architecture Letters, 2016

Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Modeling the implications of DRAM failures and protection techniques on datacenter TCO.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Characterization and analysis of a web search benchmark.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

2013
Modeling the impact of permanent faults in caches.
TACO, 2013

Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

An analytical framework for estimating TCO and exploring data center design space.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Memory array protection: check on read or check on write?
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Optimizing Data-Center TCO with Scale-Out Processors.
IEEE Micro, 2012

NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Thermal characterization of cloud workloads on a power-efficient server-on-chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Improving Branch Prediction by Considering Affectors and Affectees Correlations.
Trans. HiPEAC, 2011

CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches.
TACO, 2011

Eliminating energy of same-content-cell-columns of on-chip SRAM arrays.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

An analytical model for the calculation of the Expected Miss Ratio in faulty caches.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

RVC-based time-predictable faulty caches for safety-critical systems.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

RVC: a mechanism for time-analyzable real-time processors with faulty caches.
Proceedings of the High Performance Embedded Architectures and Compilers, 2011

2010
Performance-effective operation below Vcc-min.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

Extrinsic and Intrinsic Text Cloning.
Proceedings of the Computer Architecture, 2010

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2008
The Significance of Affectors and Affectees Correlations for Branch Prediction.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
A study of thread migration in temperature-constrained multicores.
TACO, 2007

2005
Performance implications of single thread migration on a chip multi-core.
SIGARCH Computer Architecture News, 2005

The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best.
Computer Architecture Letters, 2005

2003
Instruction-Isomorphism in Program Execution.
J. Instruction-Level Parallelism, 2003

Selecting long atomic traces for high coverage.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

2002
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Modeling Value Speculation.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001
How to compare the performance of two SMT microarchitectures.
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001

1999
Limits of Data Value Predictability.
International Journal of Parallel Programming, 1999

1998
Modeling Program Predictability.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1997
The Predictability of Data Values.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Trace Processors.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

1996
The Performance Potential of Data Dependence Speculation & Collapsing.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996


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