Yiannakis Sazeides
Orcid: 0000-0002-2624-3647
According to our database1,
Yiannakis Sazeides
authored at least 67 papers
between 1996 and 2022.
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Bibliography
2022
On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study.
IEEE Trans. Sustain. Comput., 2022
A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays.
IEEE Trans. Emerg. Top. Comput., 2022
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization.
IEEE Trans. Computers, 2021
IEEE Micro, 2021
SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Identification of an Entire Workload's CPU-Vmin from the n-First Seconds of its Execution Based on Performance Counters.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020
Performance Characterization of Simultaneous Multi-Threading and Index Partitioning for an Online Document Search Application.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
ACM Trans. Archit. Code Optim., 2019
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
IEEE Comput. Archit. Lett., 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
J. Parallel Distributed Comput., 2017
A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application.
CoRR, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures.
ACM Trans. Archit. Code Optim., 2016
IEEE Comput. Archit. Lett., 2016
Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016
Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Modeling the implications of DRAM failures and protection techniques on datacenter TCO.
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015
2013
ACM Trans. Archit. Code Optim., 2013
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
Trans. High Perform. Embed. Archit. Compil., 2011
CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches.
ACM Trans. Archit. Code Optim., 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the High Performance Embedded Architectures and Compilers, 2011
2010
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses.
Proceedings of the 7th Conference on Computing Frontiers, 2010
2008
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches.
Proceedings of the Design, Automation and Test in Europe, 2008
2007
ACM Trans. Archit. Code Optim., 2007
2005
SIGARCH Comput. Archit. News, 2005
IEEE Comput. Archit. Lett., 2005
2003
Proceedings of the 17th Annual International Conference on Supercomputing, 2003
2002
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002
2001
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001
1999
1998
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998
1997
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997
1996
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996