Itaru Hida

According to our database, Itaru Hida authored at least 3 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors.

Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2014

A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator.

Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

A restricted dynamically reconfigurable architecture for low power processors.

Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013