Tetsuya Asai
Orcid: 0000-0003-1158-9810
According to our database1,
Tetsuya Asai
authored at least 132 papers
between 1996 and 2024.
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Bibliography
2024
Int. J. Parallel Emergent Distributed Syst., March, 2024
2022
IEICE Trans. Inf. Syst., December, 2022
IEEE Trans. Circuits Syst. Video Technol., 2022
Performance of reservoir computing in a random network of single-walled carbon nanotubes complexed with polyoxometalate.
Neuromorph. Comput. Eng., 2022
2020
IEEE Trans. Circuits Syst. Video Technol., 2020
Int. J. Netw. Comput., 2020
2019
IEICE Trans. Inf. Syst., 2019
IEICE Trans. Inf. Syst., 2019
An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators.
Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band.
Proceedings of the 2019 Digital Image Computing: Techniques and Applications, 2019
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019
Proceedings of the Handbook of Memristor Networks., 2019
2018
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA.
Microprocess. Microsystems, 2018
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.
IEEE J. Solid State Circuits, 2018
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.
Complex., 2018
Proceedings of the IEEE Visual Communications and Image Processing, 2018
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
2017
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Int. J. Parallel Emergent Distributed Syst., 2017
Int. J. Parallel Emergent Distributed Syst., 2017
Int. J. Parallel Emergent Distributed Syst., 2017
Proceedings of the Artificial Intelligence XXXIV, 2017
In-memory area-efficient signal streaming processor design for binary neural networks.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the Fifth International Symposium on Computing and Networking, 2017
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017
2016
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata.
Int. J. Unconv. Comput., 2016
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
J. Inf. Process., 2015
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
IEICE Electron. Express, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Signal Amplification by Circular Single-Electron Oscillator Network with Stochastic Resonance.
Proceedings of the 8th International Conference on Bio-inspired Information and Communications Technologies, 2014
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the International Conference on High Performance Computing & Simulation, 2013
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
2012
Proceedings of the 6th International Conference on Soft Computing and Intelligent Systems (SCIS), 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator.
Int. J. Unconv. Comput., 2011
2010
A 1-muhboxW 600- hboxppm/<sup>circ</sup>hboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
J. Circuits Syst. Comput., 2010
An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs.
IEICE Trans. Electron., 2010
IEICE Trans. Electron., 2010
A behavioral model of unipolar resistive RAMs and its application to HSPICE integration.
IEICE Electron. Express, 2010
Proceedings of the Neural Information Processing. Theory and Algorithms, 2010
High performance sensor-less injection force control considering friction phenomenon.
Proceedings of the 11th IEEE International Workshop on Advanced Motion Control, 2010
2009
Proceedings of the Encyclopedia of Complexity and Systems Science, 2009
Sensorless Force Control for Injection Molding Machine Using Reaction Torque Observer Considering Torsion Phenomenon.
IEEE Trans. Ind. Electron., 2009
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs.
IEEE J. Solid State Circuits, 2009
Int. J. Nanotechnol. Mol. Comput., 2009
Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons.
Proceedings of the International Joint Conference on Neural Networks, 2009
Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits.
Proceedings of the Neural Information Processing, 16th International Conference, 2009
Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the Artificial Life Models in Hardware, 2009
2008
Int. J. Unconv. Comput., 2008
Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs.
IEICE Electron. Express, 2008
Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning.
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008
A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits.
Proceedings of the ESSCIRC 2008, 2008
Stochastic Synchronization and Array-Enhanced Coherence Resonance in a Bio-inspired Chemical Sensor Array.
Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, 2008
2007
IEEE J. Solid State Circuits, 2007
Striped and Spotted Pattern Generation on Reaction-diffusion Cellular Automata - Theory and LSI Implementation.
Int. J. Unconv. Comput., 2007
Int. J. Unconv. Comput., 2007
A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters.
Neurocomputing, 2007
Int. J. Bifurc. Chaos, 2007
Single-electron Circuits Performing Dendritic Pattern Formation with Nature-Inspired Cellular Automata.
Int. J. Bifurc. Chaos, 2007
Int. J. Bifurc. Chaos, 2007
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning.
Proceedings of the International Joint Conference on Neural Networks, 2007
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning.
Proceedings of the Neural Information Processing, 14th International Conference, 2007
2006
Int. J. Bifurc. Chaos, 2006
A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Electron. Express, 2006
IEICE Electron. Express, 2006
Proceedings of the Toward Category-Level Object Recognition, 2006
2005
Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata.
Parallel Algorithms Appl., 2005
A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA.
J. Robotics Mechatronics, 2005
Int. J. Unconv. Comput., 2005
Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model.
Int. J. Unconv. Comput., 2005
Silicon Implementation of a Chemical Reaction-diffusion Processor for Computation of Voronoi Diagram.
Int. J. Bifurc. Chaos, 2005
IEICE Trans. Electron., 2005
On the fault tolerance of a clustered single-electron neural network for differential enhancement.
IEICE Electron. Express, 2005
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller.
J. Robotics Mechatronics, 2004
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection.
Int. J. Robotics Autom., 2004
Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata.
IEICE Electron. Express, 2004
IEICE Electron. Express, 2004
Intell. Autom. Soft Comput., 2004
An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion.
IEEE Trans. Neural Networks, 2003
IEEE Trans. Neural Networks, 2003
Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses.
J. Robotics Mechatronics, 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
2002
A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics: Bridging the Digital Divide, Yasmine Hammamet, Tunisia, October 6-9, 2002, 2002
2000
Simultaneous parametric uncertainty modeling and robust control synthesis by LFT scaling.
Autom., 2000
An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000
1999
IEEE Trans. Neural Networks, 1999
A subthreshold MOS circuit for the Lotka-Volterra neural network producing the winners-share-all solution.
Neural Networks, 1999
1998
Proceedings of the Knowledge-Based Intelligent Electronic Systems, 1998
1996
A MOS circuit for a nonmonotonic neural network with excellent retrieval capabilities.
IEEE Trans. Neural Networks, 1996