Masayuki Ikebe

Orcid: 0000-0002-6770-8260

According to our database1, Masayuki Ikebe authored at least 59 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Corrections to "A Sub-Pixel Accurate Quantification of Joint Space Narrowing Progression in Rheumatoid Arthritis".
IEEE J. Biomed. Health Informatics, February, 2024

Halo Reduction in Display Systems through Smoothed Local Histogram Equalization and Human Visual System Modeling.
CoRR, 2024

A Psychological Study: Importance of Contrast and Luminance in Color to Grayscale Mapping.
CoRR, 2024

2023
A deep registration method for accurate quantification of joint space narrowing progression in rheumatoid arthritis.
Comput. Medical Imaging Graph., September, 2023

Pixel Variation Characteristics of a Global Shutter THz Imager and its Calibration Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023

A Sub-Pixel Accurate Quantification of Joint Space Narrowing Progression in Rheumatoid Arthritis.
IEEE J. Biomed. Health Informatics, 2023

A Deep Registration Method for Accurate Quantification of Joint Space Narrowing Progression in Rheumatoid Arthritis.
CoRR, 2023

2022
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark.
IEEE Trans. Circuits Syst. Video Technol., 2022

Ring-VCO-based ReLU activation function with linearity improvement for pulsed neuron circuits.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Simultaneous pixel calibration for global shutter THz imager.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Warm-cool color-based high-speed decolorization: an empirical approach for tone mapping applications.
J. Electronic Imaging, 2021

Quantification of Joint Space Width Difference on Radiography Via Phase-Only Correlation (POC) Analysis: a Phantom Study Comparing with Various Tomographical Modalities Using Conventional Margin-Contouring.
J. Digit. Imaging, 2021

2020
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA.
IEEE Trans. Circuits Syst. Video Technol., 2020

2019
FPGA-Based Annealing Processor with Time-Division Multiplexing.
IEICE Trans. Inf. Syst., 2019

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks.
IEICE Trans. Inf. Syst., 2019

A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Automatic Radiographic Quantification of Joint Space Narrowing Progression in Rheumatoid Arthritis Using POC.
Proceedings of the 16th IEEE International Symposium on Biomedical Imaging, 2019

Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band.
Proceedings of the 2019 Digital Image Computing: Techniques and Applications, 2019

3D Integrated Pixel Sensor with Silicon-on-Insulator Technology for the International Linear Collider Experiment.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA.
Microprocess. Microsystems, 2018

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.
IEEE J. Solid State Circuits, 2018

Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.
Complex., 2018

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions.
Proceedings of the IEEE Visual Communications and Image Processing, 2018

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Quantization Error-Based Regularization in Neural Networks.
Proceedings of the Artificial Intelligence XXXIV, 2017

In-memory area-efficient signal streaming processor design for binary neural networks.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Low latency divider using ensemble of moving average curves.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Exploring optimized accelerator design for binarized convolutional neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

A Time-Division Multiplexing Ising Machine on FPGAs.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

An image sensor/processor 3D stacked module featuring ThruChip interfaces.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Accelerating deep learning by binarized hardware.
Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

2016
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Bit-depth expansion for noisy contour reduction in natural images.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer.
Proceedings of the Symposium on VLSI Circuits, 2015

Halo control for LHE based local adaptive tone mapping.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

2014
Recent progress in the technology linking sensors and digital circuits.
IEICE Electron. Express, 2014

A 12-bit, 5.5-μW single-slope ADC using intermittent working TDC with multi-phase clock signals.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Accuracy improvement of histogram-based image filtering.
Proceedings of the IEEE International Conference on Image Processing, 2013

Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

60-GHz, 9-µW wake-up receiver for short-range wireless communications.
Proceedings of the ESSCIRC 2013, 2013

2012
A 11b 5.1µW multi-slope ADC with a TDC using multi-phase clock signals.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
O(1) bilateral filtering with low memory usage.
Proceedings of the International Conference on Image Processing, 2010

Column parallel single-slope ADC with time to digital converter for CMOS imager.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Local adaptive tone mapping with composite multiple gamma functions.
Proceedings of the International Conference on Image Processing, 2009

A 3.1-10.6 GHz RF CMOS circuits monolithically integrated with dipole antenna.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2007
Evaluation of Digitally Controlled PLL by Clock-Period Comparison.
IEICE Trans. Electron., 2007

2006
CMOS Image Sensor Using Negative-Feedback Resetting to Obtain Variably Smoothed Images.
IEICE Trans. Electron., 2006

2005
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata.
Parallel Algorithms Appl., 2005

A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA.
J. Robotics Mechatronics, 2005

2004
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection.
Int. J. Robotics Autom., 2004

1998
nu-MOS cellular-automaton devices for intelligent image sensors.
Proceedings of the Knowledge-Based Intelligent Electronic Systems, 1998


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