Ivan Ratkovic

Orcid: 0000-0002-0524-7227

According to our database1, Ivan Ratkovic authored at least 17 papers between 2013 and 2023.

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Bibliography

2023
Teaching computing for complex problems in civil engineering and geosciences using big data and machine learning: synergizing four different computing paradigms and four different management domains.
J. Big Data, December, 2023

Research in computing-intensive simulations for nature-oriented civil-engineering and related scientific fields, using machine learning and big data: an overview of open problems.
J. Big Data, 2023

2021
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021

2020
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chips.
CoRR, 2020

2018
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
An Integrated Vector-Scalar Design on an In-Order ARM Core.
ACM Trans. Archit. Code Optim., 2017

2016
On the design of power- and energy-efficient functional units for vector processors.
PhD thesis, 2016

A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Towards low-power embedded vector processor.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Chapter One - An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques.
Adv. Comput., 2015

Imposing coarse-grained reconfiguration to general purpose processors.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

VALib and SimpleVector: tools for rapid initial research on vector architectures.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
On the selection of adder unit in energy efficient vector processing.
Proceedings of the International Symposium on Quality Electronic Design, 2013


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