Avi Mendelson

Appl. Intell., April, 2023

Weisfeiler and Leman Go Infinite: Spectral and Combinatorial Pre-Colorings.

[BibT_eX]

[DOI]

Trans. Mach. Learn. Res., 2023

Research in computing-intensive simulations for nature-oriented civil-engineering and related scientific fields, using machine learning and big data: an overview of open problems.

[BibT_eX]

[DOI]

J. Big Data, 2023

Towards Open Scan for the Open-source Hardware.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

SCART: Simulation of Cyber Attacks for Real-Time.

[BibT_eX]

[DOI]

Kfir Girstein

Eliron Rahimi

CoRR, 2023

A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion.

[BibT_eX]

[DOI]

Suman Deb

Anupam Chattopadhyay

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

The Use of Performance-Countersto Perform Side-Channel Attacks.

[BibT_eX]

[DOI]

Ron Segev

Proceedings of the Cyber Security, Cryptology, and Machine Learning, 2023

Exploring the Limitations of the Property-based Hardware-Trojan Detection Methods.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

2022

A Design Flow and Tool for Avoiding Asymmetric Aging.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

FBM: Fast-Bit Allocation for Mixed-Precision Quantization.

[BibT_eX]

[DOI]

CoRR, 2022

Bimodal Distributed Binarized Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2022

On Recoverability of Graph Neural Network Representations.

[BibT_eX]

[DOI]

Maxim Fishman

Ron Banner

CoRR, 2022

Contrast to Divide: Self-Supervised Pre-Training for Learning with Noisy Labels.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022

2021

Loss aware post-training quantization.

[BibT_eX]

[DOI]

Yury Nahshan

Ron Banner

Mach. Learn., 2021

CAT: Compression-Aware Training for bandwidth reduction.

[BibT_eX]

[DOI]

Ron Banner

J. Mach. Learn. Res., 2021

A survey of algorithmic methods in IC reverse engineering.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2021

On Threat of Hardware Trojan to Post-Quantum Lattice-Based Schemes: A Key Recovery Attack on SABER and Beyond.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2021

Sandbox Detection Using Hardware Side Channels.

[BibT_eX]

[DOI]

Yehonatan Lusky

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020

A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2020

Towards Designing a Secure RISC-V System-on-Chip: ITUS.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2020

Asymmetric Aging Effect on Modern Microprocessors.

[BibT_eX]

[DOI]

CoRR, 2020

Self-Supervised Learning for Large-Scale Unsupervised Image Clustering.

[BibT_eX]

[DOI]

CoRR, 2020

Electromigration-Aware Architecture for Modern Microprocessors.

[BibT_eX]

[DOI]

Yinnon Stav

CoRR, 2020

HCM: Hardware-Aware Complexity Metric for Neural Network Architectures.

[BibT_eX]

[DOI]

Alex Karbachevsky

CoRR, 2020

Colored Noise Injection for Training Adversarially Robust Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2020

Secure Your SoC: Building System-an-Chip Designs for Security.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Feature Map Transform Coding for Energy-Efficient CNN Inference.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

2019

UNIQ: Uniform Noise Injection for Non-Uniform Quantization of Neural Networks.

[BibT_eX]

[DOI]

Eli Schwartz

ACM Trans. Comput. Syst., 2019

Memory-Side Protection With a Capability Enforcement Co-Processor.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2019

Energy oriented EDF for real-time systems.

[BibT_eX]

[DOI]

Gil Kedar

Israel Cidon

Int. J. Embed. Syst., 2019

Smoothed Inference for Adversarially-Trained Models.

[BibT_eX]

[DOI]

Yaniv Nemcovsky

CoRR, 2019

Towards Learning of Filter-Level Heterogeneous Compression of Convolutional Neural Networks.

[BibT_eX]

[DOI]

Yochai Zur

Itay Evron

CoRR, 2019

Security and Privacy in the Age of Big Data and Machine Learning.

[BibT_eX]

[DOI]

Computer, 2019

Rack-Scale Capabilities: Fine-Grained Protection for Large-Scale Memories.

[BibT_eX]

[DOI]

Computer, 2019

Tuning Performance via Metrics with Expectations.

[BibT_eX]

[DOI]

Ahmad Yasin

Yosi Ben-Asher

IEEE Comput. Archit. Lett., 2019

Secure Speculative Core.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

ITUS: A Secure RISC-V System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

SoK: An Overview of Algorithmic Methods in IC Reverse Engineering.

[BibT_eX]

[DOI]

Ran Ginosar

Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

Recruiting Fault Tolerance Techniques for Microprocessor Security.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

MIA: Metric Importance Analysis for Big Data Workload Characterization.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

Minimum-Weight Link-Disjoint Node-"Somewhat Disjoint" Paths.

[BibT_eX]

[DOI]

IEEE/ACM Trans. Netw., 2018

Efficient non-uniform quantizer for quantized neural network targeting reconfigurable hardware.

[BibT_eX]

[DOI]

CoRR, 2018

NICE: Noise Injection and Clamping Estimation for Neural Network Quantization.

[BibT_eX]

[DOI]

Yoav Chai

Eli Schwartz

CoRR, 2018

UNIQ: Uniform Noise Injection for the Quantization of Neural Networks.

[BibT_eX]

[DOI]

Eli Schwartz

CoRR, 2018

Rebooting Computers to Avoid Meltdown and Spectre.

[BibT_eX]

[DOI]

Computer, 2018

Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017

Using Scan Side Channel to Detect IP Theft.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

SPACE: Semi-Partitioned CachE for Energy Efficient, Hard Real-Time Systems.

[BibT_eX]

[DOI]

Gil Kedar

Israel Cidon

IEEE Trans. Computers, 2017

Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform.

[BibT_eX]

[DOI]

CoRR, 2017

Extending Amdahl's Law for Multicores with Turbo Boost.

[BibT_eX]

[DOI]

Uri Verner

IEEE Comput. Archit. Lett., 2017

ScaleSimulator: A Fast and Cycle-Accurate Parallel Simulator for Architectural Exploration.

[BibT_eX]

[DOI]

Proceedings of the 10th EAI International Conference on Simulation Tools and Techniques, 2017

Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering.

[BibT_eX]

[DOI]

Ran Ginosar

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Architectural Support for Fault Tolerance in a Teradevice Dataflow System.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2016

H-EARtH: Heterogeneous Multicore Platform Energy Management.

[BibT_eX]

[DOI]

Computer, 2016

GPUpIO: the case for I/O-driven preemption on GPUs.

[BibT_eX]

[DOI]

Lior Zeno

Mark Silberstein

Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit, 2016

Using Scan Side Channel for Detecting IP Theft.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

Optimal link-disjoint node-"somewhat disjoint" paths.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Network Protocols, 2016

2015

Power and thermal constraints of modern system-on-a-chip computer.

[BibT_eX]

[DOI]

Microelectron. J., 2015

Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck.

[BibT_eX]

[DOI]

Uri C. Weiser

IEEE Comput. Archit. Lett., 2015

Hardware Transactions in Nonvolatile Memory.

[BibT_eX]

[DOI]

Hillel Avni

Eliezer Levy

Tsvetoslava Vateva-Gurova

Proceedings of the Distributed Computing - 29th International Symposium, 2015

Establishing a Base of Trust with Performance Counters for Enterprise Workloads.

[BibT_eX]

[DOI]

Proceedings of the 2015 USENIX Annual Technical Conference, 2015

The Impact of Hypervisor Scheduling on Compromising Virtualized Environments.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

2014

TERAFLUX: Harnessing dataflow in next generation teradevices.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2014

Energy management of highly dynamic server workloads in an heterogeneous data center.

[BibT_eX]

[DOI]

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Deep-dive analysis of the data analytics workload in CloudSuite.

[BibT_eX]

[DOI]

Ahmad Yasin

Yosi Ben-Asher

Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

Batch Method for Efficient Resource Sharing in Real-Time Multi-GPU Systems.

[BibT_eX]

[DOI]

Uri Verner

Proceedings of the Distributed Computing and Networking - 15th International Conference, 2014

Scheduling periodic real-time communication in multi-GPU systems.

[BibT_eX]

[DOI]

Uri Verner

Proceedings of the 23rd International Conference on Computer Communication and Networks, 2014

2013

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Data-Parallel Computing Meets STRIPS.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Seventh AAAI Conference on Artificial Intelligence, 2013

2012

Exploring the limits of GPGPU scheduling in control flow bound applications.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2012

Scheduling processing of real-time data streams on heterogeneous multi-GPU systems.

[BibT_eX]

[DOI]

Proceedings of the 5th Annual International Systems and Storage Conference, 2012

Topic 4: High-Performance Architecture and Compilers.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

2011

DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

Using Underutilized CPU Resources to Enhance Its Reliability.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2010

Threads vs. caches: Modeling the behavior of parallel workloads.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

2009

Service level agreement for multithreaded processors.

[BibT_eX]

[DOI]

Ron Gabor

Shlomo Weiss

ACM Trans. Archit. Code Optim., 2009

Many-Core vs. Many-Thread Machines: Stay Away From the Valley.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2009

Programming model for a heterogeneous x86 platform.

[BibT_eX]

[DOI]

Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2009

Multiple clock and voltage domains for chip multi processors.

[BibT_eX]

[DOI]

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

2008

Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

A Programming Model and Architectural Extensions for Fine-Grain Parallelism.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Parallel Computing - Models, Algorithms and Applications., 2007

Trace cache sampling filter.

[BibT_eX]

[DOI]

Michael Behar

Avinoam Kolodny

ACM Trans. Comput. Syst., 2007

Fairness enforcement in switch on event multithreading.

[BibT_eX]

[DOI]

Ron Gabor

Shlomo Weiss

ACM Trans. Archit. Code Optim., 2007

Using fine grain multithreading for energy efficient computing.

[BibT_eX]

[DOI]

Alex Gontmakher

Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007

Current trends in computer architectures: multi-cores, many-cores and special-cores.

[BibT_eX]

[DOI]

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

Code Compilation for an Explicitly Parallel Register-Sharing Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

2006

Inthreads: a low granularity parallelization model.

[BibT_eX]

[DOI]

Alex Gontmakher

SIGARCH Comput. Archit. News, 2006

A PAB-Based Multi-Prefetcher Mechanism.

[BibT_eX]

[DOI]

Alexander Gendler

Yitzhak Birk

Int. J. Parallel Program., 2006

Fairness and Throughput in Switch on Event Multithreading.

[BibT_eX]

[DOI]

Ron Gabor

Shlomo Weiss

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Memory management challenges in the power-aware computing era.

[BibT_eX]

[DOI]

Proceedings of the 5th International Symposium on Memory Management, 2006

Speculative synchronization and thread management for fine granularity threads.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

2004

Power Awareness through Selective Dynamically Optimized Traces.

[BibT_eX]

[DOI]

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003

Micro-operation cache: a power aware frontend for variable instruction length ISA.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

On Estimating Optimal Performance of CPU Dynamic Thermal Management.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2003

PARROT: Power Awareness Through Selective Dynamically Optimized Traces.

[BibT_eX]

[DOI]

Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

2001

The effect of seance communication on multiprocessing systems.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2001

Dynamic techniques for load and load-use scheduling.

[BibT_eX]

[DOI]

Amir Roth

Ronny Ronen

Proc. IEEE, 2001

Coming challenges in microarchitecture and architecture.

[BibT_eX]

[DOI]

Proc. IEEE, 2001

Design of a parallel interconnect based on communication pattern considerations.

[BibT_eX]

[DOI]

Parallel Algorithms Appl., 2001

Filtering Techniques to Improve Trace-Cache Efficiency.

[BibT_eX]

[DOI]

Roni Rosner

Ronny Ronen

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000

Designing High-Performance & Reliable Superscalar Architectures: The out of Order Reliable Superscalar (O3RS) Approach.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000

1999

The "Smart" simulation environment - A tool-set to develop new cache coherency protocols.

[BibT_eX]

[DOI]

J. Syst. Archit., 1999

Design Alternatives of Multithreaded Architecture.

[BibT_eX]

[DOI]

Michael Bekerman

Int. J. Parallel Program., 1999

1998

Using Value Prediction to Increase the Power of Speculative Execution Hardware.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 1998

Improving achievable ILP through value prediction and program profiling.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1998

The Effect of Instruction Fetch Bandwidth on Value Prediction.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1997

Can Program Profiling Support Value Prediction?

[BibT_eX]

[DOI]

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Smart: An Advanced Shared-Memory Simulator - Towards a System-Level Simulation Environmen.

[BibT_eX]

[DOI]

Proceedings of the MASCOTS 1997, 1997

Cache based fault recovery for distributed systems.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '97), 1997

1996

Performance and hardware complexity tradeoffs in designing multithreaded architectures.

[BibT_eX]

[DOI]

Michael Bekerman

Gad Sheaffer

Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995

A performance analysis of Pentium processor systems.

[BibT_eX]

[DOI]

Michael Bekerman

IEEE Micro, 1995

1994

Toward a General-Purpose Multi-Stream System.

[BibT_eX]

[DOI]

Bilha Mendelson

Proceedings of the Parallel Architectures and Compilation Techniques, 1994

1991

BDG-torus union graph-an efficient algorithmically specializedparallel interconnect.

[BibT_eX]

[DOI]