Jaehyun Park

Orcid: 0000-0001-5623-6985

Affiliations:
  • Seoul National University, Department of Intelligence and Information, Korea


According to our database1, Jaehyun Park authored at least 12 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

AttAcc! Unleashing the Power of PIM for Batched Transformer-based Generative Model Inference.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands.
IEEE Comput. Archit. Lett., 2023

Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models.
IEEE Comput. Archit. Lett., 2023

How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units.
ACM Trans. Design Autom. Electr. Syst., 2022

GraNDe: Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks.
IEEE Comput. Archit. Lett., 2022

Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
TRiM: Tensor Reduction in Memory.
IEEE Comput. Archit. Lett., 2021

TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020
MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks.
IEEE Trans. Computers, 2020


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