Sukhan Lee

Affiliations:

Seoul National University, Department of Transdisciplinary Studies, South Korea

According to our database¹, Sukhan Lee authored at least 16 papers between 2015 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2022

Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM.

[BibT_eX]

[DOI]

IEEE Micro, 2022

Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer.

[BibT_eX]

[DOI]

IEEE Micro, 2022

An FPGA-based RNN-T Inference Accelerator with PIM-HBM.

[BibT_eX]

[DOI]

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

An Architecture of Sparse Length Sum Accelerator in AxDIMM.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020

MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

2019

TWiCe: preventing row-hammering by exploiting time window counters.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018

TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices.

[BibT_eX]

[DOI]

IEEE Access, 2018

3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017

Understanding power-performance relationship of energy-efficient modern DRAM devices.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Work as a team or individual: Characterizing the system-level impacts of main memory partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

2016

Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2016

Achieving One Billion Key-Value Requests per Second on a Single Server.

[BibT_eX]

[DOI]

IEEE Micro, 2016

2015

Architecting to achieve a billion requests per second throughput on a single key-value store server platform.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

CiDRA: A cache-inspired DRAM resilience architecture.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Sukhan Lee

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...