Byeongho Kim

Orcid: 0000-0002-3227-2436

According to our database1, Byeongho Kim authored at least 10 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Samsung PIM/PNM for Transfmer Based AI : Energy Efficiency on PIM/PNM Cluster.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2022
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units.
ACM Trans. Design Autom. Electr. Syst., 2022

GraNDe: Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks.
IEEE Comput. Archit. Lett., 2022

Accelerating Transformer Networks through Recomposing Softmax Layers.
Proceedings of the IEEE International Symposium on Workload Characterization, 2022

An FPGA-based RNN-T Inference Accelerator with PIM-HBM.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

An Architecture of Sparse Length Sum Accelerator in AxDIMM.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
TRiM: Tensor Reduction in Memory.
IEEE Comput. Archit. Lett., 2021

TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020
MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks.
IEEE Trans. Computers, 2020

2019
Restructuring Batch Normalization to Accelerate CNN Training.
Proceedings of Machine Learning and Systems 2019, 2019


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