Jaeil Lim

Orcid: 0009-0007-4627-9309

Affiliations:
  • Yonsei University, Seoul, South Korea


According to our database1, Jaeil Lim authored at least 13 papers between 2013 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
A New NB-LDPC Code Construction Method With Arbitrary Generalized Girth.
IEEE Trans. Commun., 2026

2025
A New Two-Tiered ECC Configuration Method for Cluster Error Correction in HBM Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

A New ECC Configuration Method for DRAM System Considering Metadata.
IEEE Trans. Computers, April, 2025

2018
Thermal Aware Test Scheduling for NTV Circuit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Reconfigurable scan architecture for test power and data volume reduction.
IEICE Electron. Express, 2017

A novel X-filling method for capture power reduction.
IEICE Electron. Express, 2017

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design.
Proceedings of the International SoC Design Conference, 2017

2016
Process variation-aware bridge fault analysis.
Proceedings of the International SoC Design Conference, 2016

2015
3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability.
ACM Comput. Surv., 2015

2014
Recovery-enhancing task scheduling for multicore processors under NBTI impact.
IEICE Electron. Express, 2014

2013
Dynamic thermal management for 3D multicore processors under process variations.
IEICE Electron. Express, 2013

Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations.
IEICE Electron. Express, 2013


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