Hyunyul Lim

According to our database1, Hyunyul Lim authored at least 14 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2020
Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks.
Sensors, 2020

2019
A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
Neural Network Reliability Enhancement Approach Using Dropout Underutilization in GPU.
Proceedings of the TENCON 2018, 2018

2017
FRESH: A New Test Result Extraction Scheme for Fast TSV Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

LARECD: Low area overhead and reliable error correction DMR architecture.
Proceedings of the International SoC Design Conference, 2017

2016
Optimized Built-In Self-Repair for Multiple Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A New 3-D Fuse Architecture to Improve Yield of 3-D Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

P-backtracking: A new scan chain diagnosis method with probability.
Proceedings of the International SoC Design Conference, 2016

2015
A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories.
IEEE Trans. Reliab., 2015

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability.
ACM Comput. Surv., 2015

Low power scan bypass technique with test data reduction.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2013
Dynamic thermal management for 3D multicore processors under process variations.
IEICE Electron. Express, 2013

Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations.
IEICE Electron. Express, 2013


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