James Burnette

According to our database, James Burnette authored at least 3 papers between 1998 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

A 2GHz, 7W (max) 64b Power^TM Microprocessor Core.

Daniel Murray, James Burnette, Brian Campbell, Mark Chung, Bruce Fernandes, Subhendra Ghosh, Rajat Goel, Greg Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, Fabian Klass, Fang Liu, Anup Mehta, Yamini Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, Sribalan Santhanam, Junji Sugisawa, Shyam Sundar, Honkai John Tam, Ricky Wen, Eric Wu, Jung-Cheng Yeh, John Yong, Sanjay Zambare

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology.

Brian Campbell, James Burnette, Naveen Javarappa, Vincent von Kaenel

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

1998

A low-cost, 300-MHz, RISC CPU with attached media processor.

Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen

IEEE J. Solid State Circuits, 1998