Daniel Murray

According to our database, Daniel Murray authored at least 9 papers between 1972 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Fuzzy logic image processing.

Adnan Shaout, Daniel Murray, Abdelwahed Motwakel

Int. J. Knowl. Eng. Data Min., 2019

2007

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems.

Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 2GHz, 7W (max) 64b Power^TM Microprocessor Core.

Daniel Murray, James Burnette, Brian Campbell, Mark Chung, Bruce Fernandes, Subhendra Ghosh, Rajat Goel, Greg Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, Fabian Klass, Fang Liu, Anup Mehta, Yamini Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, Sribalan Santhanam, Junji Sugisawa, Shyam Sundar, Honkai John Tam, Ricky Wen, Eric Wu, Jung-Cheng Yeh, John Yong, Sanjay Zambare

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.

Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr

IEEE J. Solid State Circuits, 2006

2005

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.

Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr

IEEE J. Solid State Circuits, 2005

2003

A 2× load/store pipe for a low-power 1-GHz embedded processor.

Zongjian Chen, Daniel Murray, Steve Nishimoto, Mark H. Pearce, Max Oyker, Daniel Rodriguez, Robert Rogenmoser, Dongwook (Drew) Suh, Erik Supnet, Vincent von Kaenel, George Yiu

IEEE J. Solid State Circuits, 2003

1998

A low-cost, 300-MHz, RISC CPU with attached media processor.

Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen

IEEE J. Solid State Circuits, 1998

1996

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor.

James Montanaro, Richard T. Witek, Krishna Anne, Andrew J. Black, Elizabeth M. Cooper, Daniel W. Dobberpuhl, Paul M. Donahue, Jim Eno, Gregory W. Hoeppner, David Kruckemyer, Thomas H. Lee, Peter C. M. Lin, Liam Madden, Daniel Murray, Mark H. Pearce, Sribalan Santhanam, Kathryn J. Snyder, Ray Stephany, Stephen C. Thierauf

IEEE J. Solid State Circuits, 1996

1972

Document Retrieval Based on Clustered Files.

Daniel Murray

PhD thesis, 1972