James S. Ayers
Orcid: 0000-0001-9801-3384
According to our database1,
James S. Ayers
authored at least 4 papers
between 2019 and 2025.
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Bibliography
2025
Compact PNP BJT-Based Temperature Sensor and Sub-1-V Bandgap Reference for SoC Applications in 4-nm FinFET.
IEEE J. Solid State Circuits, August, 2025
16 Arrays of 32 All-to-All Coupled CMOS Oscillators for AI Inference and Combinatorial Optimization.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2020
A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019