Anni Lu

Orcid: 0000-0002-4415-0866

According to our database¹, Anni Lu authored at least 18 papers between 2020 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

2023

Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2023

2022

Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Nonvolatile Capacitive Crossbar Array for In-Memory Computing.

[BibT_eX]

[DOI]

Adv. Intell. Syst., 2022

Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling.

[BibT_eX]

[DOI]

Gihun Choe

Prasanna Venkatesan Ravindran

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.

[BibT_eX]

[DOI]

Frontiers Artif. Intell., 2021

Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2021

Compute-in-Memory: From Device Innovation to 3D System Integration.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Compute-in-RRAM with Limited On-chip Resources.

[BibT_eX]

[DOI]

Anni Lu

Xiaochen Peng

Shimeng Yu

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Anni Lu

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