Ian A. Young
Orcid: 0000-0002-4017-5265Affiliations:
- Intel Corporation, Hillsboro, OR, USA
According to our database1,
Ian A. Young
authored at least 36 papers
between 2000 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1999, "For contributions to microprocessor circuit implementation and technology development.".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on ethw.org
On csauthors.net:
Bibliography
2023
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
2021
Gaussian Random Number Generator with Reconfigurable Mean and Variance using Stochastic Magnetic Tunnel Junctions.
CoRR, 2021
2019
A Coupled CMOS Oscillator Array for 8ns and 55pJ Inference in Convolutional Neural Networks.
CoRR, 2019
CoRR, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
RFC, August, 2018
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning.
Proceedings of the ACMSE 2018 Conference, Richmond, KY, USA, March 29-31, 2018, 2018
2017
CoRR, 2017
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
Principles and trends in quantum nano-electronics and nano-magnetics for beyond-CMOS computing.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls.
CoRR, 2016
2015
Experimental Demonstration of Efficient Spin-Orbit Torque Switching of an MTJ with sub-100 ns Pulses.
CoRR, 2015
2014
Static and Clocked Spintronic Circuit Design and Simulation With Performance Analysis Relative to CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
2013
Proc. IEEE, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
2011
A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE Commun. Mag., 2010
Analog mixed-signal circuits in advanced nano-scale CMOS technology for microprocessors and SoCs.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2007
A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2004
2003
2000
IEEE J. Solid State Circuits, 2000