Ian A. Young

According to our database1, Ian A. Young authored at least 30 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1999, "For contributions to microprocessor circuit implementation and technology development.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
Scalable energy-efficient magnetoelectric spin-orbit logic.
Nat., 2019

A Coupled CMOS Oscillator Array for 8ns and 55pJ Inference in Convolutional Neural Networks.
CoRR, 2019

Convolution Inference via Synchronization of a Coupled CMOS Oscillator Array.
CoRR, 2019

Benchmarking Physical Performance of Neural Inference Circuits.
CoRR, 2019

An Energy-Efficient Classifier via Boosted Spin Channel Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
The Entity Category Security Assertion Markup Language (SAML) Attribute Types.
RFC, August, 2018

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning.
Proceedings of the ACMSE 2018 Conference, Richmond, KY, USA, March 29-31, 2018, 2018

2017
CMOS Scaling Trends and Beyond.
IEEE Micro, 2017

Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation.
CoRR, 2017

Shannon-inspired Statistical Computing to Enable Spintronics.
CoRR, 2017

Technology Options for Beyond-CMOS.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Principles and trends in quantum nano-electronics and nano-magnetics for beyond-CMOS computing.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls.
CoRR, 2016

2015
Experimental Demonstration of Efficient Spin-Orbit Torque Switching of an MTJ with sub-100 ns Pulses.
CoRR, 2015

2014
Static and Clocked Spintronic Circuit Design and Simulation With Performance Analysis Relative to CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Convolutional Networks for Image Processing by Coupled Oscillator Arrays.
CoRR, 2014

2013
Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking.
Proc. IEEE, 2013

2012
Modeling and Design of Spintronic Integrated Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Material Targets for Scaling All Spin Logic
CoRR, 2012

All Spin Nano-magnetic State Elements
CoRR, 2012

Device Considerations for Nanophotonic CMOS Global Interconnects
CoRR, 2012

2011
Circuit Theory for Analysis and Design of Spintronic Integrated Circuits
CoRR, 2011

A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Optical I/O Technology for Tera-Scale Computing.
IEEE J. Solid State Circuits, 2010

Optical technology for energy efficient I/O in high performance computing.
IEEE Commun. Mag., 2010

Analog mixed-signal circuits in advanced nano-scale CMOS technology for microprocessors and SoCs.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2007
A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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