James S. Ayers
According to our database1,
James S. Ayers
authored at least 2 papers
between 2019 and 2020.
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Bibliography
2020
A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019