James Waldemer

According to our database1, James Waldemer authored at least 6 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2025
A Monolithic 5.7 A/mm<sup>2</sup> 91% Peak Efficiency Scalable Multistage Modular Switched Capacitor Voltage Regulator for Base Die Vertical Power Delivery in 3D-ICs.
IEEE J. Solid State Circuits, April, 2025

2024
A Monolithic 12.7 W/mm<sup>2</sup>, 92% Peak-Efficiency Switched-Capacitor DC-DC Converter Using CSCR-First Topology.
IEEE J. Solid State Circuits, December, 2024

A Monolithic 5.7A/mm<sup>2</sup> 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Integration of Si-Interposer and High Density MIM Capacitor on 2.5D Foveros Face-to-Face Architecture.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

28.4 A Monolithic 12.7W/mm<sup>2</sup> Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2020
Reliability Characterization for 12 V Application Using the 22FFL FinFET Technology.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020


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