James W. Tschanz
Orcid: 0000-0003-0317-4332Affiliations:
- Intel
According to our database1,
James W. Tschanz
authored at least 127 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
14.9 A Monolithic 10.5W/mm<sup>2</sup>600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
28.4 A Monolithic 12.7W/mm<sup>2</sup> Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Monolithic 26A/mm<sup>2</sup>Imax, 88.5% Peak-Efficiency Continuously Scalable Conversion-Ratio Switched-Capacitor DC-DC Converter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors.
IEEE J. Solid State Circuits, 2022
2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) Operation.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning.
IEEE J. Solid State Circuits, 2021
A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop.
IEEE J. Solid State Circuits, 2020
A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A Quad-Output Elastic Switched Capacitor Converter and Per-Core LDO with 87% Power Efficiency and 2.5× Core-Frequency Range Improvement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors.
IEEE J. Solid State Circuits, 2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019
A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2018
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2018
A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A Sub-cm<sup>3</sup> Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications.
IEEE J. Solid State Circuits, 2017
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating.
IEEE J. Solid State Circuits, 2017
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging.
IEEE J. Solid State Circuits, 2016
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits, 2016
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015
A fully integrated charge sharing active decap scheme for power supply noise suppression.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Error-energy analysis of hardware logarithmic approximation methods for low power applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2014
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits.
IEEE J. Solid State Circuits, 2014
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS.
IEEE J. Solid State Circuits, 2013
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.
IEEE J. Solid State Circuits, 2013
IEEE Des. Test, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
2012
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE J. Solid State Circuits, 2011
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the International Green Computing Conference 2010, 2010
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2009
IEEE Des. Test Comput., 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2007
A 256-Kb Dual-V<sub>CC</sub> SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V<sub>T</sub> CMOS process.
IEEE J. Solid State Circuits, 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2003
Dynamic sleep transistor and body bias for active leakage power control of microprocessors.
IEEE J. Solid State Circuits, 2003
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
IEEE J. Solid State Circuits, 2002
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage.
IEEE J. Solid State Circuits, 2002
IEEE Des. Test Comput., 2002
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
Proceedings of the 39th Design Automation Conference, 2002
2001
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001