Jatin N. Mistry

According to our database, Jatin N. Mistry authored at least 4 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Active Mode Subclock Power Gating.

Jatin N. Mistry, James Myers, Bashir M. Al-Hashimi, David Flynn, John Biggs, Geoff V. Merrett

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

Leakage power minimisation techniques for embedded processors.

Jatin N. Mistry

PhD thesis, 2013

2012

dRail: A Novel Physical Layout Methodology for Power Gated Circuits.

Jatin N. Mistry, John Biggs, James Myers, Bashir M. Al-Hashimi, David Flynn

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2011

Sub-clock power-gating technique for minimising leakage power during active mode.

Jatin N. Mistry, Bashir M. Al-Hashimi, David Flynn, Stephen Hill

Proceedings of the Design, Automation and Test in Europe, 2011