Javier Uceda

According to our database1, Javier Uceda authored at least 17 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to the development of switched-mode power supplies.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Black-Box Small-Signal Structure for Single-Phase and Three-Phase Electric Vehicle Battery Chargers.
IEEE Access, 2020

2019
Blackbox Polytopic Model With Dynamic Weighting Functions for DC-DC Converters.
IEEE Access, 2019

2018
Modeling Electronic Power Converters in Smart DC Microgrids - An Overview.
IEEE Trans. Smart Grid, 2018

Dynamic Assessment of COTS Converters-Based DC Integrated Power Systems in Electric Ships.
IEEE Trans. Ind. Informatics, 2018

2008
Control of Distributed Uninterruptible Power Supply Systems.
IEEE Trans. Ind. Electron., 2008

2003
Study of 3-D magnetic components by means of "double 2-D" methodology.
IEEE Trans. Ind. Electron., 2003

Harmonic reducer converter.
IEEE Trans. Ind. Electron., 2003

2000
Highly Configurable Control Boards: A Tool and a Design Experience.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

1999
An alternative to supply DC voltages with high power factor.
IEEE Trans. Ind. Electron., 1999

1998
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models.
Proceedings of the 1998 Design, 1998

1997
The discontinuous conduction mode Sepic and Cuk power factor preregulators: analysis and design.
IEEE Trans. Ind. Electron., 1997

An integrated battery charger/discharger with power-factor correction.
IEEE Trans. Ind. Electron., 1997

1996
Magnetic element modeling tool (MEMT) from POWERCAD ESPRIT project.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Model generation of test logic for macrocell based designs.
Proceedings of the conference on European design automation, 1996

A fault model for VHDL descriptions at the register transfer level.
Proceedings of the conference on European design automation, 1996

Timing optimization by an improved redundancy addition and removal technique.
Proceedings of the conference on European design automation, 1996

1995
Low voltage Power Electronics.
J. Circuits Syst. Comput., 1995


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