Eduardo de la Torre

According to our database1, Eduardo de la Torre authored at least 83 papers between 1993 and 2021.

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Bibliography

2021
A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT.
IEEE Internet Things J., 2021

2020
An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems.
IEEE Access, 2020

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs.
IEEE Access, 2020

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation.
IEEE Access, 2020

Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping.
Microprocess. Microsystems, 2019

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming.
Genet. Program. Evolvable Mach., 2019

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression.
IEEE Access, 2019

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems.
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC.
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

2018
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo<sup>3</sup> Framework.
Sensors, 2018

A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images.
Remote. Sens., 2018

Accelerating the evolution of a systolic array-based evolvable hardware system.
Microprocess. Microsystems, 2018

A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017
Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Cross-layer design of reconfigurable cyber-physical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2016
A scalable H.264/AVC deblocking filter architecture.
J. Real Time Image Process., 2016

Introduction to the Special Section on FPGAs Technology and Applications.
Comput. Electr. Eng., 2016

2015
Letter from the guest editors of the special issue on DCIS 2014.
Microprocess. Microsystems, 2015

Introduction to Special issue on Reconfigurable computing and FPGAs.
Microprocess. Microsystems, 2015

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis.
IET Inf. Secur., 2015

Execution modeling in self-aware FPGA-based architectures for efficient resource management.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Message from the chairs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic.
Microprocess. Microsystems, 2014

Introduction to Special issue on FPGA Devices and Applications.
Microprocess. Microsystems, 2014

Introduction to the special issue on FPGA Technology and Applications.
Comput. Electr. Eng., 2014

Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm.
Proceedings of the Information Security Practice and Experience, 2014

A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

Power-aware multi-objective evolvable hardware system on an FPGA.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing.
IEEE Trans. Computers, 2013

A scalable evolvable hardware processing array.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

A self-adaptive image processing application based on evolvable and scalable hardware.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

A noise-agnostic self-adaptive image processing application based on evolvable hardware.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks.
Sensors, 2012

Power management techniques in an FPGA-based WSN node for high performance applications.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Automatic generation of identical routing pairs for FPGA implemented DPL logic.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

2011
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Reconfigurable Networks on Chip: DRNoC architecture.
J. Syst. Archit., 2010

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors.
Int. J. Distributed Sens. Networks, 2010

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Modular Peripheral to Support Self-Reconfiguration in SoCs.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Generic Systolic Array for Run-Time Scalable Cores.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2008
A Fast Emulation-Based NoC Prototyping Framework.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007
A digital system to emulate wireless networks.
IET Comput. Digit. Tech., 2007

Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Modular Architecture for Nodes in Wireless Sensor Networks.
J. Univers. Comput. Sci., 2006

Partial Reconfiguration for Core Reallocation and Flexible Communications.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Flexible Core Reallocation for Virtex II Structures.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion.
Proceedings of the Field Programmable Logic and Application, 2004

2000
Highly Configurable Control Boards: A Tool and a Design Experience.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

1999
Design methodologies based on hardware description languages.
IEEE Trans. Ind. Electron., 1999

1998
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models.
Proceedings of the 1998 Design, 1998

1996
Model generation of test logic for macrocell based designs.
Proceedings of the conference on European design automation, 1996

1993
Distributed Implementation of an ATPG System Using Dynamic Fault Allocation.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

A dynamic communication strategy for the distributed ATPG system DPLATON.
Proceedings of the European Design Automation Conference 1993, 1993


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