Kenneth M. Butler

According to our database1, Kenneth M. Butler authored at least 57 papers between 1988 and 2017.

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Bibliography

2017
Accurate ADC testing with significantly relaxed instrumentation including large cumulative jitter.
Proceedings of the IEEE International Test Conference, 2017

2016
Statistical outlier screening as a test solution health monitor.
Proceedings of the 2016 IEEE International Test Conference, 2016

What we know after twelve years developing and deploying test data analytics solutions.
Proceedings of the 2016 IEEE International Test Conference, 2016

2015
A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.
Proceedings of the 2014 International Test Conference, 2014

2013
Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Efficient Process Shift Detection and Test Realignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Physics-Based Low-Cost Test Technique for High Voltage LDMOS.
J. Electron. Test., 2013

Test data analytics - Exploring spatial and test-item correlations in production test data.
Proceedings of the 2013 IEEE International Test Conference, 2013

A design-for-reliability approach based on grading library cells for aging effects.
Proceedings of the 2013 IEEE International Test Conference, 2013

Adaptive quality binning for analog circuits.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Early prediction of NBTI effects using RTL source code analysis.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Adaptive multidimensional outlier analysis for analog and mixed signal circuits.
Proceedings of the 2011 IEEE International Test Conference, 2011

Die-level adaptive test: Real-time test reordering and elimination.
Proceedings of the 2011 IEEE International Test Conference, 2011

Test cost reduction through performance prediction using virtual probe.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
Power Supply Noise: A Survey on Effects and Research.
IEEE Des. Test Comput., 2010

Adaptive test flow for mixed-signal/RF circuits using learned information from device under test.
Proceedings of the 2011 IEEE International Test Conference, 2010

Adapting to adaptive testing.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Multidimensional Test Escape Rate Modeling.
IEEE Des. Test Comput., 2009

Quality improvement and cost reduction using statistical outlier methods.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
Modeling Test Escape Rate as a Function of Multiple Coverages.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs.
IEEE Des. Test Comput., 2007

2006
Guest Editor's Introduction: ITC Helps Get More Out of Test.
IEEE Des. Test Comput., 2006

2004
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Sure You Can Get to 100 DPPM in Deep Submicron, But It'll Cost Ya.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs.
IEEE Des. Test Comput., 2003

A Case Study of IR-Drop in Structured At-Speed Testing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges .
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Is ITC Bored with Board Test?
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Facilitating Rapid First Silicon Debug.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Defect-Oriented Testing and Defective-Part-Level Prediction.
IEEE Des. Test Comput., 2001

An analysis of power reduction techniques in scan testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A case study on the implementation of the Illinois Scan Architecture.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

An empirical study on the effects of test type ordering on overall test efficiency.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Estimating the Economic Benefits of DFT.
IEEE Des. Test Comput., 1999

REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Correlation of logical failures to a suspect process step.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Expediting ramp-to-volume production.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
On applying non-classical defect models to automated diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

The stuck-at fault: it ain't over 'til it's over.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Automated Diagnosis in Testing and Failure Analysis.
IEEE Des. Test Comput., 1997

An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Bridging Fault Diagnosis in the Absence of Physical Information.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Integrating Automated Diagnosis into the Testing and Failure Analysis Operations.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Test Generation and Design for Test for a Large Multiprocessing DSP.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Deep Submicron: Is Test Up to the Challenge?
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
Correlating defect level to final test fault coverage for modular structured designs [microcontroller family].
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

1992
The roles of controllability and observability in design for test.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991
Exact ordered binary decision diagram size when representing classes of symmetric functions.
J. Electron. Test., 1991

Fast functional evaluation of candidate OBDD variable orderings.
Proceedings of the conference on European design automation, 1991

Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams.
Proceedings of the 28th Design Automation Conference, 1991

1990
The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1988
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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