Jean A. Peperstraete

According to our database1, Jean A. Peperstraete authored at least 35 papers between 1982 and 1998.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1998
Rapid prototyping of an adaptive noise canceler using GRAPE.
Signal Processing, 1998

Code Generation for Compiled Bit-True Simulation of DSP Applications.
Proceedings of the 11th International Symposium on System Synthesis, 1998

1997
Data routing in dataflow graphs.
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Cycle-static dataflow.
IEEE Trans. Signal Processing, 1996

Implementing DSP applications on heterogeneous targets using minimal size data buffers.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Cyclo-Dynamic Dataflow.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

Global Approach for Compiled Bit-True Simulation of DSP Systems.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
PDG: A process-level debugger for concurrent programs in the GRAPE parallel programming environment.
Future Generation Comp. Syst., 1995

Grape-II: A System-Level Prototyping Environment for DSP Applications.
IEEE Computer, 1995

Hardware-software codesign with GRAPE.
Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

A Loader for Injured Massively Parallel Regular Networks.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

A User-Adaptable Fault Tolerant Motor Controller using an Argument Flow Multiprocessor System.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

A User-triggered Checkpointing Library for Computationintensive Applications.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

Cyclo-static data flow.
Proceedings of the 1995 International Conference on Acoustics, 1995

Compile-time scheduling with resource-constraints.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

Kernel services approach to fault-masking in real-time applications.
Proceedings of the 7th Euromicro Workshop on Real-Time Systems, 1995

1994
Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks.
Sci. Ann. Cuza Univ., 1994

Fault-Tolerant Compact Routing Based on Reduced Structural Information in Wormhole-Switching Based Networks.
Proceedings of the Structural Information and Communication Complexity, 1994

Geometric parallelism and cyclo-static data flow in GRAPE-II.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994

Buffer memory requirements in DSP applications.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994

PDG: A Portable Process-Level Debugger for CSP-Style Parallel Programs.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

VLSI complexity reduction by piece-wise approximation of the sigmoid function.
Proceedings of the ESANN 1994, 1994

Control of a Dead-time Process by a Fuzzy Algorithm.
Proceedings of the 12st IASTED International Conference on Applied Informatics, 1994

1993
Design of a processing board for a programmable multi-VSP system.
VLSI Signal Processing, 1993

PDG: a process-level debugger for concurrent programs in the GRAPE rapid prototyping environment.
Proceedings of the Fourth International Workshop on Rapid System Prototyping, 1993

Development of a load balancing tool for the GRAPE rapid prototyping environment.
Proceedings of the Fourth International Workshop on Rapid System Prototyping, 1993

Efficient decomposition of comparison and its applications.
Proceedings of the ESANN 1993, 1993

1992
GRAPE-II: a tool for the rapid prototyping of multi-rate asynchronous DSP applications on heterogeneous multiprocessors.
Proceedings of the Third International Workshop on Rapid System Prototyping, 1992

1991
Rapid Prototyping for DSP Systems with Multiprocessors.
IEEE Design & Test of Computers, 1991

A Powerful Hig-Level Debugger for Parallel Programs.
Proceedings of the Parallel Computation, First International ACPC Conference, Salzburg, Austria, September 30, 1991

1990
Parallel processing enables the real-time emulation of DSP ASICs.
Proceedings of the First International Workshop on Rapid System Prototyping, 1990

1987
An Integrated Software-Hardware Multiprocesor Project.
Proceedings of the International Conference on Parallel Processing, 1987

1983
Implementing Streams on a Data Flow Computer System With Paged Memory
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

1982
A data flow architecture with a paged memory system.
Proceedings of the 9th International Symposium on Computer Architecture (ISCA 1982), 1982


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