Rudy Lauwereins

According to our database1, Rudy Lauwereins authored at least 182 papers between 1987 and 2018.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to data flow models in real-time prototyping".

Timeline

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Bibliography

2018
Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017
Impact of CSI Feedback Strategies on LTE Downlink and Reinforcement Learning Solutions for Optimal Allocation.
IEEE Trans. Vehicular Technology, 2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Wave pipelining for majority-based beyond-CMOS technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection.
Signal Processing Systems, 2016

Inversion optimization in Majority-Inverter Graphs.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Scalable HetNet interference management and the impact of limited channel state information.
EURASIP J. Wireless Comm. and Networking, 2015

Area and routing efficiency of SWD circuits compared to advanced CMOS.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014
Derivative-Based Scale Invariant Image Feature Detector With Error Resilience.
IEEE Trans. Image Processing, 2014

Scalable LTE interference mitigation solution for HetNet deployment.
Proceedings of the 2014 IEEE Wireless Communications and Networking Conference Workshops, 2014

Exploiting transport-block constraints in LTE improves downlink performance.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

The value of feedback for LTE resource allocation.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

Multi-objective genetic algorithm downlink resource allocation in LTE: Exploiting the cell-edge vs. Cell-center trade-off.
Proceedings of the 21st IEEE Symposium on Communications and Vehicular Technology in the Benelux, 2014

System-level assessment and area evaluation of Spin Wave logic circuits.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Towards approaching near-optimal MIMO detection performance ONAC-programmable baseband processor.
Proceedings of the IEEE International Conference on Acoustics, 2014

NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Interfacing to living cells.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Exploration of Lattice Reduction Aided Soft-Output MIMO Detection on a DLP/ILP Baseband Processor.
IEEE Trans. Signal Processing, 2013

Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

SIFER: Scale-Invariant Feature Detector with Error Resilience.
International Journal of Computer Vision, 2013

A computationally efficient soft-output Lattice Reduction-aided Selective Spanning Sphere Decoder for wireless MIMO systems.
Proceedings of the 24th IEEE Annual International Symposium on Personal, 2013

2012
Constant Time Joint Bilateral Filtering Using Joint Integral Histograms.
IEEE Trans. Image Processing, 2012

Supplementary Proof for "Equalization Algorithms in the Frequency Domain for Continuous Phase Modulations".
IEEE Trans. Communications, 2012

A Generic Framework for Optimizing Digital Intensive Harmonic Rejection Receivers.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Reduced Complexity On-chip IQ-Imbalance Self-Calibration.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Analysis of power efficiency of schedulers in LTE.
Proceedings of the 19th IEEE Symposium on Communications and Vehicular Technology in the Benelux, 2012

Lattice Reduction aided Selective Spanning with Fast Enumeration for soft-output MIMO detection.
Proceedings of the 20th European Signal Processing Conference, 2012

Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Biomedical electronics serving as physical environmental and emotional watchdogs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Real-Time and Accurate Stereo: A Scalable Approach With Bitwise Fast Voting on CUDA.
IEEE Trans. Circuits Syst. Video Techn., 2011

Robust Low Complexity Corner Detector.
IEEE Trans. Circuits Syst. Video Techn., 2011

Performance analysis of distributed ZF beamforming in the presence of CFO.
EURASIP J. Wireless Comm. and Networking, 2011

Beamforming techniques for enabling spatial-reuse in MCCA 802.11s networks.
EURASIP J. Wireless Comm. and Networking, 2011

A cross-based filter for fast edge-preserving smoothing.
Proceedings of the Real-Time Image and Video Processing 2011, 2011

Energy-throughput simulation approach for heterogeneous LTE scenarios.
Proceedings of the 8th International Symposium on Wireless Communication Systems, 2011

Impact of carrier frequency offset in cooperative phase shift beamforming.
Proceedings of the 19th European Signal Processing Conference, 2011

Performance analysis of the distributed ZF beamformer in the presence of carrier frequency offset.
Proceedings of the 19th European Signal Processing Conference, 2011

Hybrid lattice reduction algorithm and its implementation on an SDR baseband processor for LTE.
Proceedings of the 19th European Signal Processing Conference, 2011

2010
Novel block constructions using an intrafix for CPM with frequency domain equalization.
IEEE Trans. Wireless Communications, 2010

Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements.
ACM Trans. Embedded Comput. Syst., 2010

Joint integral histograms and its application in stereo matching.
Proceedings of the International Conference on Image Processing, 2010

Robust low complexity feature tracking.
Proceedings of the International Conference on Image Processing, 2010

Maximum SINR-Based Beamforming for the MISO OFDM Interference Channel.
Proceedings of IEEE International Conference on Communications, 2010

Lococo: low complexity corner detector.
Proceedings of the IEEE International Conference on Acoustics, 2010

2009
Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments.
Signal Processing Systems, 2009

Low-complexity linear frequency domain equalization for continuous phase modulation.
IEEE Trans. Wireless Communications, 2009

Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts.
ACM Trans. Design Autom. Electr. Syst., 2009

Accurate and efficient stereo matching with robust piecewise voting.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Robust stereo matching with fast Normalized Cross-Correlation over shape-adaptive regions.
Proceedings of the International Conference on Image Processing, 2009

A Flexible Antenna Selection Scheme for 60 GHz Multi-Antenna Systems Using Interleaved ADCs.
Proceedings of IEEE International Conference on Communications, 2009

Joint Transmit and Receive Analog Beamforming in 60 GHz MIMO Multipath Channels.
Proceedings of IEEE International Conference on Communications, 2009

Maximum SINR-based beamforming for the MISO interference channel.
Proceedings of the 17th European Signal Processing Conference, 2009

Tap and transmit antenna correlation based precoding for MIMO-OFDM systems.
Proceedings of the 17th European Signal Processing Conference, 2009

2008
A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing.
IEEE Micro, 2008

A New Symbol Block Construction for CPM with Frequency Domain Equalization.
Proceedings of IEEE International Conference on Communications, 2008

Applying frequency domain equalization to precoded CPM.
Proceedings of the IEEE International Conference on Acoustics, 2008

Spectral regrowth analysis of band-limited offset-QPSK.
Proceedings of the IEEE International Conference on Acoustics, 2008

Complexity Reduction of High-Performance Frequency Domain Equalization for CPM.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

Spectrum Sensing over SIMO Multi-Path Fading Channels Based on Energy Detection.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Comparison of OQPSK and CPM for Communications at 60 GHz with a Nonideal Front End.
EURASIP J. Wireless Comm. and Networking, 2007

Sensitivity to Front-End Non-Idealities of Low PAPR Modulation Schemes for Communications at 60 GHz.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

The Generalized Linear Decomposition of Multilevel CPM Signals.
Proceedings of the IEEE International Conference on Acoustics, 2007

Low-Complexity Frequency Domain Equalization Receiver for Continuous Phase Modulation.
Proceedings of the Global Communications Conference, 2007

Adaptive mapping to resource availability for dynamic wavelet-based applications.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

2006
Platform independent optimisation of multi-resolution 3D content to enable universal media access.
The Visual Computer, 2006

Eliminating CPU overhead for on-the-fly content adaptation with MPEG-4 wavelet subdivision surfaces.
IEEE Trans. Consumer Electronics, 2006

Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications.
VLSI Signal Processing, 2005

Architecture Exploration for a Reconfigurable Architecture Template.
IEEE Design & Test of Computers, 2005

Pareto based optimization of multi-resolution geometry for real time rendering.
Proceedings of the Proceeding of the Tenth International Conference on 3D Web Technology, 2005

Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform.
Proceedings of the Integrated Circuit and System Design, 2005

Wireless platforms: GOPS for cents and MilliWatts.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Run-time support for heterogeneous multitasking on reconfigurable SoCs.
Integration, 2004

3D graphics rendering time modeling and control for mobile terminals.
Proceedings of the Proceeding of the Ninth International Conference on 3D Web Technology, 2004

Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

High-Level Data-Access Analysis for Characterisation of (Sub)task-Level Parallelism in Java.
Proceedings of the 9th International Workshop on High-Level Programming Models and Supportive Environments (HIPS 2004), 2004

Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation.
Proceedings of the Field Programmable Logic and Application, 2004

Design-Time Data-Access Analysis for Parallel Java Programs with Shared-Memory Communication Model.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

QOS Aware HW/SW Partitioning on Run-time Reconfigurable Multimedia Platforms.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study.
Proceedings of the 2004 Design, 2004

How Can System-Level Design Solve the Interconnect Technology Scaling Problem?
Proceedings of the 2004 Design, 2004

System level design technology for realizing an ambient intelligent environment.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Instruction buffering exploration for low energy VLIWs with instruction clusters.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications.
ACM Trans. Design Autom. Electr. Syst., 2003

A formant filtered physical model for wind instruments.
IEEE Trans. Speech and Audio Processing, 2003

Editorial.
EURASIP J. Adv. Sig. Proc., 2003

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level.
Proceedings of the Integrated Circuit and System Design, 2003

Instruction Buffering Exploration for Low Energy Embedded Processors.
Proceedings of the Integrated Circuit and System Design, 2003

Designing an Operating System for a Heterogeneous Reconfigurable So.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A framework for mapping scalable networked applications on run-time reconfigurable platforms.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Visual and Complexity Analysis of the Extended Loop Subdivision Scheme.
Proceedings of the 2003 International Conference on Geometric Modeling and Graphics, 2003

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Networks on Chip as Hardware Components of an OS for Reconfigurable Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Low Power Coarse-Grained Reconfigurable Instruction Set Processor.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

Panel Title: Reconfigurable Computing - Different Perspectives.
Proceedings of the 2003 Design, 2003

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip.
Proceedings of the 2003 Design, 2003

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling.
Proceedings of the 2003 Design, 2003

2002
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective.
IEEE Trans. Software Eng., 2002

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
The Journal of Supercomputing, 2002

A QoS Framework for Interactive 3D Applications.
Proceedings of the 10-th International Conference in Central Europe on Computer Graphics, 2002

Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

A Fast QoS Adaptation Algorithm for MPEG-4 Multimedia Applications.
Proceedings of the Protocols and Systems for Interactive Distributed Multimedia, 2002

Measurement of guitar string coupling.
Proceedings of the 2002 International Computer Music Conference, 2002

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2002

Creating a World of Smart Re-configurable Devices.
Proceedings of the Field-Programmable Logic and Applications, 2002

Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.
Proceedings of the Field-Programmable Logic and Applications, 2002

Reconfigurable SoC - What Will it Look Like?
Proceedings of the 2002 Design, 2002

Data Reuse Exploration Techniques for Loop-Dominated Application.
Proceedings of the 2002 Design, 2002

2001
Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs.
IEEE Design & Test of Computers, 2001

DF*: Modeling Dynamic Process Creation and Events for Interactive Multimedia Applications.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

Design and Implementation of a Data Stabilizing Software Tool.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

The Recovery Language Approach for Software-Implemented Fault Tolerance.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

Parameter estimation for dual-polarization plucked string models.
Proceedings of the 2001 International Computer Music Conference, 2001

Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2001

CRISP: A Template for Reconfigurable Instruction Set Processors.
Proceedings of the Field-Programmable Logic and Applications, 2001

A SW/HW Interface API for Java/FPGA Co-Designed Applets.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Task concurrency management methodology summary.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Virtual Java/FPGA interface for networked reconfiguration.
Proceedings of ASP-DAC 2001, 2001

2000
Transformations of a 3D Image Reconstruction Algorithm for Data Transfer and Storage Optimisation.
Design Autom. for Emb. Sys., 2000

Reconfigurable Instruction Set Processors: A Survey.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

The TIRAN approach to reusing software implemented fault tolerance.
Proceedings of the Eight Euromicro Workshop on Parallel and Distributed Processing, 2000

Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Systematic Data Reuse Exploration Methodology for Irregular Access Patterns.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Task Concurrency Management Experiment for Power-Efficient Speed-up of Embedded MPEG4 IM1 Player.
Proceedings of the 2000 International Workshop on Parallel Processing, 2000

A Novel Distributed Algorithm for High-Throughput and Scalable Gossiping.
Proceedings of the High-Performance Computing and Networking, 8th International Conference, 2000

An Algorithm for Tolerating Crash Failures in Distributed Systems.
Proceedings of the 7th IEEE International Symposium on Engineering of Computer-Based Systems (ECBS 2000), 2000

1999
Transformations of a 3D Image Reconstruction Algorithm for Data Transfer and Storage Optimization.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

A framework backbone for software fault tolerance in embedded parallel applications.
Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999

TIRAN: Flexible and Portable Fault Tolerance Solutions for Cost Effective Dependable Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

A Software Library, A Control Backbone and User-Specified Recovery Strategies to Enhance the Dependability of Embedded Systems.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
Rapid prototyping of an adaptive noise canceler using GRAPE.
Signal Processing, 1998

Software tool combining fault masking with user-defined recovery strategies.
IEE Proceedings - Software, 1998

Code Generation of Data Dominated DSP Applications for FPGA Targets.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

A hypermedia distributed application for monitoring and fault-injection in embedded fault-tolerant parallel programs.
PDP, 1998

Code Generation for Compiled Bit-True Simulation of DSP Applications.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Stable Memory in Substation Automation: A Case Study.
Proceedings of the Digest of Papers: FTCS-28, 1998

The EFTOS Voting Farm: A Software Tool for Fault Masking in Message Passing Parallel Environments.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
Data routing in dataflow graphs.
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

Prototyping of the Receiver Unit for a Broadband Access Network.
Proceedings of the 10th International Symposium on System Synthesis, 1997

User-triggered checkpointing: system-independent and scalable application recovery.
Proceedings of the Second IEEE Symposium on Computers and Communications (ISCC 1997), 1997

An Application-Level Dependable Technique for Farmer-Worker Parallel Programs.
Proceedings of the High-Performance Computing and Networking, 1997

EFTOS: A Software Framework for More Dependable Embedded HPC Applications.
Proceedings of the Euro-Par '97 Parallel Processing, 1997

Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Cycle-static dataflow.
IEEE Trans. Signal Processing, 1996

Implementing DSP applications on heterogeneous targets using minimal size data buffers.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Cyclo-Dynamic Dataflow.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

Global Approach for Compiled Bit-True Simulation of DSP Systems.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
PDG: A process-level debugger for concurrent programs in the GRAPE parallel programming environment.
Future Generation Comp. Syst., 1995

Grape-II: A System-Level Prototyping Environment for DSP Applications.
IEEE Computer, 1995

A Compact Fault-tolerant, Deadlock-free, Minimal Routing Algorithm for n-Dimensional Wormhole Switching Based Meshes.
Proceedings of the Structure, Information and Communication Complexity, 1995

Hardware-software codesign with GRAPE.
Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

A Loader for Injured Massively Parallel Regular Networks.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

A User-Adaptable Fault Tolerant Motor Controller using an Argument Flow Multiprocessor System.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

A User-triggered Checkpointing Library for Computationintensive Applications.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

The Consistent File-Status in a User-Triggered Checkpointing Approach.
Proceedings of the Parallel Computing: State-of-the-Art and Perspectives, 1995

Cyclo-static data flow.
Proceedings of the 1995 International Conference on Acoustics, 1995

Reconfiguration of massively parallel systems.
Proceedings of the High-Performance Computing and Networking, 1995

Compile-time scheduling with resource-constraints.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

Kernel services approach to fault-masking in real-time applications.
Proceedings of the 7th Euromicro Workshop on Real-Time Systems, 1995

1994
Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks.
Sci. Ann. Cuza Univ., 1994

On the design and implementation of broadcast and global combine operations using the postal model.
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994

Fault-Tolerant Compact Routing Based on Reduced Structural Information in Wormhole-Switching Based Networks.
Proceedings of the Structural Information and Communication Complexity, 1994

Geometric parallelism and cyclo-static data flow in GRAPE-II.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994

Buffer memory requirements in DSP applications.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994

The FTMPS-Project: Design and Implementation of Fault-Tolerance Techniques for Massively Parallel Systems.
Proceedings of the High-Performance Computing and Networking, 1994

PDG: A Portable Process-Level Debugger for CSP-Style Parallel Programs.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

VLSI complexity reduction by piece-wise approximation of the sigmoid function.
Proceedings of the ESANN 1994, 1994

1993
Design of a processing board for a programmable multi-VSP system.
VLSI Signal Processing, 1993

PDG: a process-level debugger for concurrent programs in the GRAPE rapid prototyping environment.
Proceedings of the Fourth International Workshop on Rapid System Prototyping, 1993

Development of a load balancing tool for the GRAPE rapid prototyping environment.
Proceedings of the Fourth International Workshop on Rapid System Prototyping, 1993

Efficient decomposition of comparison and its applications.
Proceedings of the ESANN 1993, 1993

1992
GRAPE-II: a tool for the rapid prototyping of multi-rate asynchronous DSP applications on heterogeneous multiprocessors.
Proceedings of the Third International Workshop on Rapid System Prototyping, 1992

1991
Rapid Prototyping for DSP Systems with Multiprocessors.
IEEE Design & Test of Computers, 1991

A Powerful Hig-Level Debugger for Parallel Programs.
Proceedings of the Parallel Computation, First International ACPC Conference, Salzburg, Austria, September 30, 1991

1990
Parallel processing enables the real-time emulation of DSP ASICs.
Proceedings of the First International Workshop on Rapid System Prototyping, 1990

1987
An Integrated Software-Hardware Multiprocesor Project.
Proceedings of the International Conference on Parallel Processing, 1987


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