Jean Jimenez

According to our database1, Jean Jimenez authored at least 10 papers between 2010 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Symmetrical ESD protection for advanced CMOS technology dedicated to 100 GHz RF application.
Microelectron. Reliab., 2013

ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control.
Proceedings of the ESSCIRC 2013, 2013

2012
Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology.
Microelectron. Reliab., 2012

High swing low capacitance ESD RF protections in advanced CMOS technologies.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

BIMOS transistor and its applications in ESD protection in advanced CMOS technology.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
Reliability impact due to high current, lattice and hot carriers temperatures on β<sup>(2×2)</sup> matrix ESD power devices for advanced CMOS technologies.
Microelectron. Reliab., 2011

A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node.
Microelectron. Reliab., 2011

2010
Inventory of silicon signatures induced by CDM event on deep sub-micronic CMOS-BICMOS technologies.
Microelectron. Reliab., 2010


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