Philippe Galy
According to our database1,
Philippe Galy
authored at least 37 papers
between 2001 and 2023.
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Bibliography
2023
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses.
CoRR, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
2022
Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
IEEE Access, 2019
Proceedings of the IEEE International Reliability Physics Symposium, 2019
10Gbps Length adaptive on-chip RF serial link for Network on Chips and Multiprocessor chips applications.
Proceedings of the International Conference on IC Design and Technology, 2019
Compact MOS Structure & Design for Ion-Ioff Thermal control in 28nm UTBB FD-SOI CMOS technology.
Proceedings of the International Conference on IC Design and Technology, 2019
1T1C Ultra low power relative Thermal-Voltage sensor in 28nm UTBB FD-SOI CMOS technology for standard, spatial and quantum applications.
Proceedings of the International Conference on IC Design and Technology, 2019
Proceedings of the 49th European Solid-State Device Research Conference, 2019
2018
Simulation, characterization and implementation of a new SCR-based device with a turn-off capability for EOS-immune ESD power supply clamps in advanced CMOS technology nodes.
Microelectron. Reliab., 2018
Optimized in situ heating control on a new MOS device structure in 28nm UTBB FD-SOI CMOS technology.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2017
Exploration of robustness limits and ESD EMI impact in a protection device for advanced CMOS technology.
Microelectron. Reliab., 2017
Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
2016
On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology.
Microelectron. Reliab., 2016
Preliminary results on TFET - Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technology.
Proceedings of the International Conference on IC Design and Technology, 2016
2015
Coupled electro-magnetic field & Lorentz force effects in silicon and metal for ESD investigation in transient and harmonic regimes.
Microelectron. Reliab., 2015
Integrated front-end/back-end simulation of electromagnetic fields, Lorentz force effects and fast current surges in microelectronic protection devices.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Computation of Self-Induced Magnetic Field Effects Including the Lorentz Force for Fast-Transient Phenomena in Integrated-Circuit Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
New modular bi-directional power-switch and self ESD protected in 28nm UTBB FDSOI advanced CMOS technology.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
2013
Symmetrical ESD protection for advanced CMOS technology dedicated to 100 GHz RF application.
Microelectron. Reliab., 2013
ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control.
Proceedings of the ESSCIRC 2013, 2013
2012
Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology.
Microelectron. Reliab., 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
2011
Reliability impact due to high current, lattice and hot carriers temperatures on β<sup>(2×2)</sup> matrix ESD power devices for advanced CMOS technologies.
Microelectron. Reliab., 2011
A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node.
Microelectron. Reliab., 2011
2010
Inventory of silicon signatures induced by CDM event on deep sub-micronic CMOS-BICMOS technologies.
Microelectron. Reliab., 2010
Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm.
Microelectron. Reliab., 2010
2009
Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress.
Microelectron. Reliab., 2009
2006
Microelectron. Reliab., 2006
2004
Experimental measurements and 3D simulation of the parasitic lateral bipolar transistor triggering within a single finger gg-nMOS under ESD.
Microelectron. Reliab., 2004
2002
Experimental and 3D simulation correlation of a gg-nMOS transistor under high current pulse.
Microelectron. Reliab., 2002
2001
Simulation and experimental comparison of GGNMOS and LVTSCR protection cells under ElectroStatic Discharges.
Microelectron. Reliab., 2001