Jerry Backer

According to our database1, Jerry Backer authored at least 8 papers between 2007 and 2017.

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Bibliography

2017
Secure and Flexible Trace-Based Debugging of Systems-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2017

2016
SIGDROP: Signature-based ROP Detection using Hardware Performance Counters.
CoRR, 2016

2015
Secure design-for-debug for Systems-on-Chip.
Proceedings of the 2015 IEEE International Test Conference, 2015

A secure design-for-test infrastructure for lifetime security of SoCs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2012
Balancing performance and fault detection for GPGPU workloads.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2007
The effect of memory bandwidth on processor performance.
Proceedings of the Richard Tapia Celebration of Diversity in Computing Conference 2007, 2007


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