Ramesh Karri

IEEE Trans. Computers, 2006

A High-Speed Hardware Architecture for Universal Message Authentication Code.

[BibT_eX]

[DOI]

David A. McGrew

IEEE J. Sel. Areas Commun., 2006

Quantum-Dot Cellular Automata Design Guideline.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

Topology aware mapping of logic functions onto nanowire-based crossbar architectures.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Divide-and-concatenate: an architecture-level optimization technique for universal hash functions.

[BibT_eX]

[DOI]

David A. McGrew

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Design of a High-Performance RSVP-TE Hardware Signaling Accelerator.

[BibT_eX]

[DOI]

H. Wang

Malathi Veeraraghavan

T. Li

IEEE J. Sel. Areas Commun., 2005

A High Speed Architecture for Galois/Counter Mode of Operation (GCM).

[BibT_eX]

[DOI]

Sambit Mishra

IACR Cryptol. ePrint Arch., 2005

On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only).

[BibT_eX]

[DOI]

Nikhil Joshi

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Fault tolerant nanoelectronic processor architectures.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A heterogeneous built-in self-repair approach using system-level synthesis flexibility.

[BibT_eX]

[DOI]

Inki Hong

IEEE Trans. Reliab., 2004

Fault secure datapath synthesis using hybrid time and hardware redundancy.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

High speed architectures for Leviathan: a binary tree based stream cipher.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2004

Scan Based Side Channel Attack on Data Encryption Standard.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2004

Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Low Cost Concurrent Error Detection for the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A hardware-accelerated implementation of the RSVP-TE signaling protocol.

[BibT_eX]

[DOI]

Haobo Wang

Malathi Veeraraghavan

Tao Li

Proceedings of IEEE International Conference on Communications, 2004

Concurrent Error Detection Schemes for Involution Ciphers.

[BibT_eX]

[DOI]

Nikhil Joshi

Proceedings of the Cryptographic Hardware and Embedded Systems, 2004

2003

Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2003

Optimizing the Energy Consumed by Secure Wireless Sessions - Wireless Transport Layer Security Case Study.

[BibT_eX]

Mob. Networks Appl., 2003

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher.

[BibT_eX]

[DOI]

Microelectron. J., 2003

Divide and Concatenate: A Scalable Hardware Architecture for Universal MAC.

[BibT_eX]

[DOI]

David A. McGrew

IACR Cryptol. ePrint Arch., 2003

Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Parity-Based Concurrent Error Detection in Symmetric Block Ciphers.

[BibT_eX]

[DOI]

Grigori Kuznetsov

Michael Gössel

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Modeling energy efficient secure wireless networks using network simulation.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2003

Nano, quantum, and molecular computing: are we ready for the validation and test challenges?

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

An investigation into the design of energy-efficient session negotiation protocols for wireless networks.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2003

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers.

[BibT_eX]

[DOI]

Grigori Kuznetsov

Michael Gössel

Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

2002

Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis.

[BibT_eX]

[DOI]

Israel Koren

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Minimizing energy consumption of secure wireless session with QoS constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2002

Exploiting Idle Cycles for Algorithm Level Re-Computing.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

Guest editor's introduction to special section on high-level design validation and test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Architectures and protocols that enable new applications on optical networks.

[BibT_eX]

[DOI]

Malathi Veeraraghavan

IEEE Commun. Mag., 2001

Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Idle Cycles Based Concurrent Error Detection of RC6 Encryption.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

Power optimization using divide-and-conquer techniques for minimization of the number of operations.

[BibT_eX]

[DOI]

Inki Hong

ACM Trans. Design Autom. Electr. Syst., 1999

Built in self test: a complete test solution for telecommunication systems.

[BibT_eX]

[DOI]

Nilanjan Mukherjee

Tapan J. Chakraborty

IEEE Commun. Mag., 1999

1998

High-reliability, low-energy microarchitecture synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures.

[BibT_eX]

[DOI]

Nilanjan Mukherjee

J. Electron. Test., 1998

Guest Editors' Introduction: Online VLSI Testing.

[BibT_eX]

Michael Nicolaidis

IEEE Des. Test Comput., 1998

Versatile BIST: an integrated approach to on-line/off-line BIST.

[BibT_eX]

[DOI]

Nilanjan Mukherjee

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Heterogeneous BISR-approach using System Level Synthesis Flexibility.

[BibT_eX]

[DOI]

Inki Hong

Proceedings of the ASP-DAC '98, 1998

1997

A Parameterized VHDL Library for On-Line Testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

Synthesis of Application Specific Programmable Processors.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 1996

Automatic Synthesis of Self-Recovering VLSI Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

Computer-Aided Design of Fault-Tolerant VLSI Systems.

[BibT_eX]

[DOI]

Karin Högstedt

IEEE Des. Test Comput., 1996

Heterogeneous built-in resiliency of application specific programmable processors.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Configurable Spare Processors: A New Approach to System Level-Fault Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

Electromigration Reliability Enhancement via Bus Activity Distribution.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Simultaneous scheduling and binding for power minimization during microarchitecture synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Synthesis of Reliable Application Specific Heterogeneous Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Phantom redundancy: a high-level synthesis approach for manufacturability.

[BibT_eX]

[DOI]

Israel Koren

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Switch level hot-carrier reliability enhancement of VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994

Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Synthesis of fault-tolerant and real-time microarchitectures.

[BibT_eX]

[DOI]

J. Syst. Softw., 1994

Rapid prototyping of fault-tolerant VLSI systems.

[BibT_eX]

[DOI]

Karin Högstedt

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Allocation and Binding During Fault-Secure Microarchitecture Synthesis.

[BibT_eX]

[DOI]

Sergei Sokolov

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Simulated annealing based yield enhancement of layouts.

[BibT_eX]

[DOI]

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

Optimal Self-Recovering Microarchitecture Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS-23, 1993

High-Level Synthesis of Fault-Secure Microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

High-Level Synthesis of Self-Recovering MicroArchitectures.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS-22, 1992

Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

ALPS: An Algorithm for Pipeline Data Path Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

1988

A security imbedded authentication protocol.

[BibT_eX]

[DOI]