Ramesh Karri

According to our database1, Ramesh Karri authored at least 264 papers between 1991 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

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On csauthors.net:

Bibliography

2020
Anomaly Detection in Real-Time Multi-Threaded Processes Using Hardware Performance Counters.
IEEE Trans. Information Forensics and Security, 2020

A Theoretical Study of Hardware Performance Counters-Based Malware Detection.
IEEE Trans. Information Forensics and Security, 2020

Synthesis of Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2020

2019
Toward Secure Microfluidic Fully Programmable Valve Array Biochips.
IEEE Trans. VLSI Syst., 2019

Reversible Circuits: IC/IP Piracy Attacks and Countermeasures.
IEEE Trans. VLSI Syst., 2019

Black-Hat High-Level Synthesis: Myth or Reality?
IEEE Trans. VLSI Syst., 2019

CAD-Base: An Attack Vector into the Electronics Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2019

Bio-Protocol Watermarking on Digital Microfluidic Biochips.
IEEE Trans. Information Forensics and Security, 2019

Locking the Design of Building Blocks for Quantum Circuits.
ACM Trans. Embedded Comput. Syst., 2019

Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Security Assessment of Micro-Electrode-Dot-Array Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits.
JETC, 2019

Split Manufacturing-Based Register Transfer-Level Obfuscation.
JETC, 2019

NIST Post-Quantum Cryptography- A Hardware Evaluation Study.
IACR Cryptology ePrint Archive, 2019

Hardware Trojans Inspired IP Watermarks.
IEEE Design & Test, 2019

Public Plug-in Electric Vehicles + Grid Data: Is a New Cyberattack Vector Viable?
CoRR, 2019

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection.
CoRR, 2019

Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Can Multi-Layer Microfluidic Design Methods Aid Bio-Intellectual Property Protection?
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Stealthy Rootkits in Smart Grid Controllers.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Desieve the Attacker: Thwarting IP Theft in Sieve-Valve-based Biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

High-Level Synthesis of Benevolent Trojans.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and Defenses.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

PREEMPT: PReempting Malware by Examining Embedded Processor Traces.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Security Assessment of Microfluidic Immunoassays.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

Can Monitoring System State + Counting Custom Instruction Sequences Aid Malware Detection?
Proceedings of the 28th IEEE Asian Test Symposium, 2019

Execution of provably secure assays on MEDA biochips to thwart attacks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
DPFEE: A High Performance Scalable Pre-Processor for Network Security Systems.
IEEE Trans. Multi-Scale Computing Systems, 2018

Process-Aware Covert Channels Using Physical Instrumentation in Cyber-Physical Systems.
IEEE Trans. Information Forensics and Security, 2018

Secure Randomized Checkpointing for Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Hardware Trojan Detection Using the Order of Path Delay.
JETC, 2018

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis.
Embedded Systems Letters, 2018

Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices.
CoRR, 2018

Securing IJTAG against data-integrity attacks.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Abetting Planned Obsolescence by Aging 3D Networks-on-Chip.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Shadow attacks on MEDA biochips.
Proceedings of the International Conference on Computer-Aided Design, 2018

IC/IP piracy assessment of reversible logic.
Proceedings of the International Conference on Computer-Aided Design, 2018

Hardware Trojan detection using path delay order encoding with process variation tolerance.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Locking of biochemical assays for digital microfluidic biochips.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Tamper-resistant pin-constrained digital microfluidic biochips.
Proceedings of the 55th Annual Design Automation Conference, 2018

TAO: techniques for algorithm-level obfuscation during high-level synthesis.
Proceedings of the 55th Annual Design Automation Conference, 2018

Process-Aware Side Channel Shaping and Watermarking for Cyber-Physical Systems.
Proceedings of the 2018 Annual American Control Conference, 2018

2017
Secure and Flexible Trace-Based Debugging of Systems-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2017

Automotive Electrical and Electronic Architecture Security via Distributed In-Vehicle Traffic Monitoring.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Guest Editors' Introduction: Cyber-Physical Systems Security and Privacy.
IEEE Design & Test, 2017

Towards Reverse Engineering Reversible Logic.
CoRR, 2017

On the Difficulty of Inserting Trojans in Reversible Computing Architectures.
CoRR, 2017

Process-aware side channel monitoring for embedded control system security.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Research Challenges in Security-Aware Physical Design.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Security Trade-Offs in Microfluidic Routing Fabrics.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Fingerprinting Field Programmable Gate Arrays.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

TAINT: Tool for Automated INsertion of Trojans.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Optimal checkpointing for secure intermittently-powered IoT devices.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization.
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, 2017

Emerging (un-)reliability based security threats and mitigations for embedded systems: special session.
Proceedings of the 2017 International Conference on Compilers, 2017

Security Implications of Cyberphysical Flow-Based Microfluidic Biochips.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach.
IEEE Trans. VLSI Syst., 2016

Hardware Trojans: Lessons Learned after One Decade of Research.
ACM Trans. Design Autom. Electr. Syst., 2016

Malicious Firmware Detection with Hardware Performance Counters.
IEEE Trans. Multi-Scale Computing Systems, 2016

Can Algorithm Diversity in Stream Cipher Implementation Thwart (Natural and) Malicious Faults?
IEEE Trans. Emerging Topics Comput., 2016

Security Assessment of Cyberphysical Digital Microfluidic Biochips.
IEEE/ACM Trans. Comput. Biology Bioinform., 2016

On Improving the Security of Logic Locking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Reusing Hardware Performance Counters to Detect and Identify Kernel Control-Flow Modifying Rootkits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Hardware Performance Counter-Based Malware Identification and Detection with Adaptive Compressive Sensing.
TACO, 2016

The Cybersecurity Landscape in Industrial Control Systems.
Proceedings of the IEEE, 2016

Guest Editorial Special Issue on Secure and Trustworthy Computing.
JETC, 2016

Cybersecurity for Control Systems: A Process-Aware Perspective.
IEEE Design & Test, 2016

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Securing digital microfluidic biochips by randomizing checkpoints.
Proceedings of the 2016 IEEE International Test Conference, 2016

Securing pressure measurements using SensorPUFs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

FPGA Trust Zone: Incorporating trust and reliability into FPGA designs.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Security engineering of nanostructures and nanomaterials.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Controlling your control flow graph.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Can flexible, domain specific programmable logic prevent IP theft?
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Microfluidic encryption of on-chip biochemical assays.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
Belling the CAD: Toward Security-Centric Electronic System Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Guest Editorial Special Section on Hardware Security and Trust.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Fault Analysis-Based Logic Encryption.
IEEE Trans. Computers, 2015

Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors.
IEEE Trans. Computers, 2015

MAGIC: Malicious Aging in Circuits/Cores.
TACO, 2015

Reliable Integrity Checking in Multicore Processors.
TACO, 2015

Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications.
Proceedings of the IEEE, 2015

Security analysis of concurrent error detection against differential fault analysis.
J. Cryptographic Engineering, 2015

Secure design-for-debug for Systems-on-Chip.
Proceedings of the 2015 IEEE International Test Conference, 2015

A secure design-for-test infrastructure for lifetime security of SoCs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Exploiting small leakages in masks to turn a second-order attack into a first-order attack.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Deep Packet Field Extraction Engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systems.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Security implications of cyberphysical digital microfluidic biochips.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

ConFirm: Detecting Firmware Modifications in Embedded Systems using Hardware Performance Counters.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Simulation and analysis of negative-bias temperature instability aging on power analysis attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Detecting malicious modifications of data in third-party intellectual property cores.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Detecting Kernel Control-Flow Modifying Rootkits.
Proceedings of the Network Science and Cybersecurity, 2014

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling.
IEEE Trans. Emerging Topics Comput., 2014

A Primer on Hardware Security: Models, Methods, and Metrics.
Proceedings of the IEEE, 2014

Regaining Trust in VLSI Design: Design-for-Trust Techniques.
Proceedings of the IEEE, 2014

Trustworthy Hardware [Scanning the Issue].
Proceedings of the IEEE, 2014

NREPO: Normal Basis Recomputing with Permuted Operands.
IACR Cryptology ePrint Archive, 2014

Low-Cost Concurrent Error Detection for GCM and CCM.
J. Electronic Testing, 2014

Detection, diagnosis, and repair of faults in memristor-based memories.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Hot topic session 12A: Split manufacturing - IARPA's TIC program.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

AES design space exploration new line for scan attack resiliency.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Test-mode-only scan attack and countermeasure for contemporary scan architectures.
Proceedings of the 2014 International Test Conference, 2014

Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Shielding and securing integrated circuits with sensors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

New scan attacks against state-of-the-art countermeasures and DFT.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Test-mode-only scan attack using the boundary scan chain.
Proceedings of the 19th IEEE European Test Symposium, 2014

Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Approximating the age of RF/analog circuits through re-characterization and statistical estimation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Recomputing with Permuted Operands: A Concurrent Error Detection Approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Invariance-Based Concurrent Error Detection for Advanced Encryption Standard.
IACR Cryptology ePrint Archive, 2013

Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach.
IEEE Design & Test, 2013

A study on the effectiveness of Trojan detection techniques using a red team blue team approach.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Sneak-path Testing of Memristor-based Memories.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

New scan-based attack using only the test mode.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

VLSI testing based security metric for IC camouflaging.
Proceedings of the 2013 IEEE International Test Conference, 2013

High-level synthesis for security and trust.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Scan attack in presence of mode-reset countermeasure.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

On design vulnerability analysis and trust benchmarks development.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Sneak path testing and fault modeling for multilevel memristor-based memories.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Hardware security: threat models and metrics.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Reconciling the IC test and security dichotomy.
Proceedings of the 18th IEEE European Test Symposium, 2013

Run-time detection of hardware Trojans: The processor protection unit.
Proceedings of the 18th IEEE European Test Symposium, 2013

Is split manufacturing secure?
Proceedings of the Design, Automation and Test in Europe, 2013

NumChecker: detecting kernel control-flow modifying rootkits by using hardware performance counters.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Security analysis of integrated circuit camouflaging.
Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

Hardware and embedded security in the context of internet of things.
Proceedings of the CyCAR'13, 2013

Hardware security strategies exploiting nanoelectronic circuits.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Guest Editorial Integrated Circuit and System Security.
IEEE Trans. Information Forensics and Security, 2012

Architecture Support for Dynamic Integrity Checking.
IEEE Trans. Information Forensics and Security, 2012

An Energy-Efficient Memristive Threshold Logic Circuit.
IEEE Trans. Computers, 2012

Leveraging Memristive Systems in the Construction of Digital Logic Circuits.
Proceedings of the IEEE, 2012

Nanoelectronic Solutions for Hardware Security.
IACR Cryptology ePrint Archive, 2012

Provably Secure Concurrent Error Detection Against Differential Fault Analysis.
IACR Cryptology ePrint Archive, 2012

Nano-PPUF: A Memristor-Based Security Primitive.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A Survey of Microarchitecture Support for Embedded Processor Security.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A high-performance, low-overhead microarchitecture for secure program execution.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Engineering crossbar based emerging memory technologies.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Balancing performance and fault detection for GPGPU workloads.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Logic encryption: A fault analysis perspective.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Security analysis of logic obfuscation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Scan-based attacks on linear feedback shift register based stream ciphers.
ACM Trans. Design Autom. Electr. Syst., 2011

Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges.
IEEE Computer, 2011

Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge.
IEEE Computer, 2011

Security-aware SoC test access mechanisms.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Design and analysis of ring oscillator based Design-for-Trust technique.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

An Approach to Tolerate Process Related Variations in Memristor-Based Applications.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Parallel memristors: Improving variation tolerance in memristive digital circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Blue team red team approach to hardware trust assessment.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Improving GPU Robustness by making use of faulty parts.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Are hardware performance counters a cost effective way for integrity checking of programs.
Proceedings of the sixth ACM workshop on Scalable trusted computing, 2011

2010
Attacks and Defenses for JTAG.
IEEE Design & Test of Computers, 2010

Trustworthy Hardware: Identifying and Classifying Hardware Trojans.
IEEE Computer, 2010

Memristor based programmable threshold logic array.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Towards a comprehensive and systematic classification of hardware Trojans.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Compact hardware architectures for BLAKE and LAKE hash functions.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Feasibility study of dynamic Trusted Platform Module.
Proceedings of the 28th International Conference on Computer Design, 2010

Sensor Physical Unclonable Functions.
Proceedings of the HOST 2010, 2010

SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers.
Proceedings of the HOST 2010, 2010

2009
Logic Mapping in Crossbar-Based Nanoarchitectures.
IEEE Design & Test of Computers, 2009

2007
Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

The Robust QCA Adder Designs Using Composable QCA Building Blocks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Towards Nanoelectronics Processor Architectures.
J. Electronic Testing, 2007

Design automation for hybrid CMOS-nonoelectronics crossbars.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations.
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007

Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Secure Scan: A Design-for-Test Architecture for Crypto Chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Micropreemption synthesis: an enabling mechanism for multitask VLSI systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks.
IEEE Trans. Computers, 2006

A High-Speed Hardware Architecture for Universal Message Authentication Code.
IEEE Journal on Selected Areas in Communications, 2006

Quantum-Dot Cellular Automata Design Guideline.
IEICE Transactions, 2006

Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.
Proceedings of the 11th European Test Symposium, 2006

Topology aware mapping of logic functions onto nanowire-based crossbar architectures.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Divide-and-concatenate: an architecture-level optimization technique for universal hash functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Design of a High-Performance RSVP-TE Hardware Signaling Accelerator.
IEEE Journal on Selected Areas in Communications, 2005

A High Speed Architecture for Galois/Counter Mode of Operation (GCM).
IACR Cryptology ePrint Archive, 2005

On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths.
Proceedings of the 2005 Design, 2005

Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Fault tolerant nanoelectronic processor architectures.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A heterogeneous built-in self-repair approach using system-level synthesis flexibility.
IEEE Trans. Reliability, 2004

Fault secure datapath synthesis using hybrid time and hardware redundancy.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

High speed architectures for Leviathan: a binary tree based stream cipher.
Microprocessors and Microsystems, 2004

Scan Based Side Channel Attack on Data Encryption Standard.
IACR Cryptology ePrint Archive, 2004

Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Low Cost Concurrent Error Detection for the Advanced Encryption Standard.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A hardware-accelerated implementation of the RSVP-TE signaling protocol.
Proceedings of IEEE International Conference on Communications, 2004

Concurrent Error Detection Schemes for Involution Ciphers.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2004

2003
Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths.
IEEE Trans. Reliability, 2003

Optimizing the Energy Consumed by Secure Wireless Sessions - Wireless Transport Layer Security Case Study.
MONET, 2003

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher.
Microelectron. J., 2003

Divide and Concatenate: A Scalable Hardware Architecture for Universal MAC.
IACR Cryptology ePrint Archive, 2003

Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks.
Proceedings of the Integrated Circuit and System Design, 2003

Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Parity-Based Concurrent Error Detection in Symmetric Block Ciphers.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Modeling energy efficient secure wireless networks using network simulation.
Proceedings of IEEE International Conference on Communications, 2003

Nano, quantum, and molecular computing: are we ready for the validation and test challenges?
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

An investigation into the design of energy-efficient session negotiation protocols for wireless networks.
Proceedings of the Global Telecommunications Conference, 2003

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

2002
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique.
IEEE Trans. VLSI Syst., 2002

Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Minimizing energy consumption of secure wireless session with QoS constraints.
Proceedings of the IEEE International Conference on Communications, 2002

Exploiting Idle Cycles for Algorithm Level Re-Computing.
Proceedings of the 2002 Design, 2002

2001
Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs.
ACM Trans. Design Autom. Electr. Syst., 2001

Guest editor's introduction to special section on high-level design validation and test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Idle Cycles Based Concurrent Error Detection of RC6 Encryption.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers.
Proceedings of the 38th Design Automation Conference, 2001

2000
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors.
IEEE Trans. Computers, 2000

Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Power optimization using divide-and-conquer techniques for minimization of the number of operations.
ACM Trans. Design Autom. Electr. Syst., 1999

Built in self test: a complete test solution for telecommunication systems.
IEEE Communications Magazine, 1999

1998
High-reliability, low-energy microarchitecture synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures.
J. Electronic Testing, 1998

Guest Editors' Introduction: Online VLSI Testing.
IEEE Design & Test of Computers, 1998

Versatile BIST: an integrated approach to on-line/off-line BIST.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Heterogeneous BISR-approach using System Level Synthesis Flexibility.
Proceedings of the ASP-DAC '98, 1998

1997
A Parameterized VHDL Library for On-Line Testing.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study.
Proceedings of the 34st Conference on Design Automation, 1997

Synthesis of Application Specific Programmable Processors.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors.
IEEE Trans. Reliability, 1996

Automatic Synthesis of Self-Recovering VLSI Systems.
IEEE Trans. Computers, 1996

Computer-Aided Design of Fault-Tolerant VLSI Systems.
IEEE Design & Test of Computers, 1996

Heterogeneous built-in resiliency of application specific programmable processors.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Configurable Spare Processors: A New Approach to System Level-Fault Tolerance.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis.
Proceedings of the 33st Conference on Design Automation, 1996

Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing.
Proceedings of the 33st Conference on Design Automation, 1996

Electromigration Reliability Enhancement via Bus Activity Distribution.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Synthesis of Reliable Application Specific Heterogeneous Multiprocessors.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Phantom redundancy: a high-level synthesis approach for manufacturability.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Switch level hot-carrier reliability enhancement of VLSI circuits.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures.
IEEE Trans. VLSI Syst., 1994

Synthesis of fault-tolerant and real-time microarchitectures.
Journal of Systems and Software, 1994

Rapid prototyping of fault-tolerant VLSI systems.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Allocation and Binding During Fault-Secure Microarchitecture Synthesis.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Simulated annealing based yield enhancement of layouts.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Optimal Self-Recovering Microarchitecture Synthesis.
Proceedings of the Digest of Papers: FTCS-23, 1993

High-Level Synthesis of Fault-Secure Microarchitectures.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
High-Level Synthesis of Self-Recovering MicroArchitectures.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs.
Proceedings of the Digest of Papers: FTCS-22, 1992

Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs.
Proceedings of the 29th Design Automation Conference, 1992

1991
ALPS: An Algorithm for Pipeline Data Path Synthesis.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991


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