Jerzy J. Dabrowski

Affiliations:
  • Linkoping University, Department of Electrical Engineering, Sweden


According to our database1, Jerzy J. Dabrowski authored at least 33 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2020
One-Bit ΣΔ-Encoded Stimulus Generation for On-Chip ADC Test.
J. Circuits Syst. Comput., 2020

2019
Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test.
J. Electron. Test., 2019

2016
Tunable selective receiver front end with impedance transformation filtering.
Int. J. Circuit Theory Appl., 2016

2015
Two-Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique.
Integr., 2015

Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Clock phase imbalance and phase noise in RF N-path filters.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2013
Highly linear open-loop output driver design for high speed capacitive DACs.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

Blocker and image reject low-IF frontend.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Focused calibration for advanced RF test with embedded RF detectors.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Wideband RF detector design for high performance on-chip test.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011
Low noise transconductance amplifier design for continuous-time ΣΔ wideband frontend.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

On-chip spectral test for high-speed ADCs by ΣΔ technique.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Built-in Loopback Test for IC RF Transceivers.
IEEE Trans. Very Large Scale Integr. Syst., 2010

On-Chip Stimulus Generator for Gain, Linearity, and Blocking Profile Test of Wideband RF Front Ends.
IEEE Trans. Instrum. Meas., 2010

Two-tone PLL for on-chip IP3 test.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
On-chip stimuli generation for ADC dynamic test by ΣΔ technique.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2007
A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
LNA design for on-chip RF test.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

SC filter for RF down conversion with wideband image rejection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005

Techniques for sensitizing RF path under SER test.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Fault modeling of RF blocks based on noise analysis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Mixed Loopback BiST for RF Digital Transceivers.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
Lookback BiST for RF front-ends in digital transceivers.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

BiST Model for IC RF-Transceiver Front-End.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Efficient post-layout timing verification via RLC trees and explicit PWL timing integration.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2000
Efficient interconnect timing analysis via piecewise linear technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique.
Proceedings of the 1999 Design, 1999

1995
Functional-level analog macromodeling with piecewise linear signals.
Proceedings of the Proceedings EURO-DAC'95, 1995

1992
Efficient timing verification via mixed-mode technique.
Microprocess. Microprogramming, 1992


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