Christer Svensson

Affiliations:
  • Linköping University, Sweden


According to our database1, Christer Svensson authored at least 66 papers between 1983 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2004, "For contributions to single phase clocking and high speed CMOS circuits.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

2014
Power Consumption of Integrated Low-Power Receivers.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Ultra Low Power Wake-Up Radio Using Envelope Detector and Transmission Line Voltage Transformer.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

2012
Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Design and Analysis of a Class-D Stage With Harmonic Suppression.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011
A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Power consumption bounds for SAR ADCs.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Envelope detector sensitivity and blocking characteristics.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE.
Proceedings of the ESSCIRC 2008, 2008

2007
Analog Power Modelling.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus.
Proceedings of the International Symposium on System-on-Chip, 2007

A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

An on-chip delay- and skew-insensitive multicycle communication scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

SC filter for RF down conversion with wideband image rejection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Well-behaved global on-chip interconnect.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Synchronous latency-insensitive design for multiple clock domain.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A high-level dynamic-error model of a pipelined analog-to-digital converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Robust multi-phase clock generation with reduced jitter.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A scalable and robust rail-to-rail delay cell for DLLs.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.
Proceedings of the Integrated Circuit and System Design, 2004

A new mesochronous clocking scheme for synchronization in SoC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2 GB/S decision feedback equalizer in 3.3 V 0.35 µM CMOS.
Proceedings of the Second IASTED International Conference on Circuits, 2004

Timing closure through a globally synchronous, timing partitioned design methodology.
Proceedings of the 41th Design Automation Conference, 2004

Synchronous Latency Insensitive Design.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
A 1.6 GHz downconversion sampling mixer in CMOS.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Full-custom vs. standard-cell design flow: an adder case study.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Electrical interconnects revitalized.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A 1 GHz linearized CMOS track-and-hold circuit.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Application of Knowledge-based System in a B-to-B Environment.
Proceedings of the Internet and Multimedia Systems and Applications, 2002

2001
Modeling of dynamic errors in algorithmic A/D converters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

3V CMOS 0.35 µ transimpedance receiver for optical applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Low power mixed analog-digital signal processing.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

GLMC: interconnect length estimation by growth-limited multifold clustering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A layout-based schematic method for very high-speed CMOS cell design.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems.
IEEE Trans. Parallel Distributed Syst., 1999

Methodology of layout based schematic and its usage in efficient high performance CMOS design.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High speed multistage CMOS clock buffers with pulse width control loop.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High speed interface for system-on-chip design by self-tested self-synchronization.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A novel mixed analog/digital MAC unit implemented with SC technique suitable for fully programmable narrow-band FIR filter applications.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A leakage-tolerant multi-phase keeper for wide domino circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Low power and low voltage CMOS digital circuit techniques.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Self-Synchronized Vector Transfer for High Speed Parallel Systems.
Proceedings of the International Conference on Parallel and Distributed Systems, 1998

Efficient High-Speed CMOS Design by Layout Based Schematic Method.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1996
VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept.
IEEE Trans. Very Large Scale Integr. Syst., 1996

1994
5.8Gb/s 16: 1 Multiplexer and 1: 16 Demultiplexer Using 1.2µm BiCMOS.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Single-chip image sensors with a digital processor array.
J. VLSI Signal Process., 1993

Ultra high speed CMOS design.
Proceedings of the VLSI 93, 1993

A sensor array for phase and amplitude detection of synchronous modulated light sources.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


1992
Performance of Synchronous and Asynchronous Schemes for VLSI Systems.
IEEE Trans. Computers, 1992

1990
Single-Chip High-Speed Computation of Optical Flow.
Proceedings of IAPR Workshop on Machine Vision Applications, 1990

1988
Switch-level simulation and the pass transistor EXOR gate.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987
Fully Dynamic Switch-Level Simulation of CMOS Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1986
Signal resynchronization in VLSI systems.
Integr., 1986

1984
NORCHIP, a silicon brokers model.
Integr., 1984

1983
VLSI physics.
Integr., 1983


  Loading...