Jiahao Lu

Orcid: 0000-0002-5793-4010

Affiliations:
  • Huazhong University of Science and Technology, School of Integrated Circuits, Wuhan, China


According to our database1, Jiahao Lu authored at least 24 papers between 2019 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2025
An Efficient and Reconfigurable Post-Quantum Crypto-Processor for SPHINCS+.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025

2024
Super-K: A Superscalar CRYSTALS-KYBER Processor Based on Efficient Arithmetic Array.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques.
IEEE J. Solid State Circuits, September, 2024

A High Speed Post-Quantum Crypto-Processor for Crystals-Dilithium.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A 206.4 dBc/Hz FoMT Class-F23 VCO using nonlinear-capacitance-transforming technique.
Microelectron. J., 2024

An Efficient and Configurable Hardware Architecture of Polynomial Modular Operation for CRYSTALS-Kyber and Dilithium.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

A Lightweight Folded Keccak-Based SHA-3 for Resource-Constrained Embedded Security.
Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024

A Timing Attack Resistant Lightweight Post-Quantum Crypto-Processor for SPHINCS+.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 40nm 1.26µ/Op Energy-Efficient CRYSTALS-KYBER Post-Quantum Crypto-Processor with Comprehensive Side Channel Security Analysis and Countermeasures.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A Flexible and High-Performance Lattice-Based Post-Quantum Crypto Secure Coprocessor.
IEEE Trans. Ind. Informatics, 2023

Multi-Probability Hash-based Random Number Generator for Post-Quantum Cryptography.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Hybrid Hardware-Software Architecture for Quantum Secure IoT Embedded Systems.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD RISC-V Coprocessor Based on Customized Vector Instruction-Set Extension.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 40nm $\boldsymbol{2.76}\boldsymbol{\mu}\mathbf{J}/\mathbf{Op}$ Energy-Efficient Secure Post-Quantum Crypto-Processor for Crystals-Kyber on Module-LWE.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
An Efficient Unstructured Sparse Convolutional Neural Network Accelerator for Wearable ECG Classification Device.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 325-μW step-16 digital-sensor based on dual-delay-chain in 180-nm CMOS.
Microelectron. J., 2022

Efficient hardware design of a deep U-net model for pixel-level ECG classification in healthcare device.
Microelectron. J., 2022

An Instruction-configurable Post-quantum Cryptographic Processor towards NTRU.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

A High Throughput and Configurable Pseudo-random Number Extension Generator for Lattice-based Post-quantum Cryptography.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
Efficient Hardware Architecture of Convolutional Neural Network for ECG Classification in Wearable Healthcare Device.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

An Efficient Hardware Architecture for Epileptic Seizure Detection using EEG Signals based on 1D-CNN.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A Flexible and Generic Gaussian Sampler With Power Side-Channel Countermeasures for Quantum-Secure Internet of Things.
IEEE Internet Things J., 2020

2019
A Fully Integrated HF RFID Tag Chip With LFSR-based Light-weight Tripling Mutual Authentication Protocol.
IEEE Access, 2019

A Configurable Architecture of ANN in Hardware with Resource-Efficient Reusable Neuron.
Proceedings of the 13th IEEE International Conference on ASIC, 2019


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