Yuejun Zhang

According to our database1, Yuejun Zhang authored at least 33 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2020
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020

65 nm sub-threshold logic standard cell library using quasi-Schmitt-trigger design scheme and inverse narrow width effect aware sizing.
IET Circuits Devices Syst., 2020

2019
A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Design of anti-key leakage camouflage gate circuit for reverse engineering based on dummy vias.
Microelectron. J., 2019

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

Design of Crosstalk NAND Gate Circuit Based on Interconnect Coupling Capacitance.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Design of Aging Detection Sensor Based on Voltage Comparison.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 96kb, 0.36V, Energy-Efficient 8T-SRAM with Column-Selection and Shared Buffer-Foot Techniques for EEG Processor.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Orthogonal Algorithm for Key Management in Hardware Obfuscation.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process.
Microelectron. J., 2018

Design of Delayed Ternary PUF Circuit Based on CNFET.
Proceedings of the 24th Asia-Pacific Conference on Communications, 2018

2017
A multi-port low-power current mode PUF using MOSFET current-division deviation in 65 nm technology.
Microelectron. J., 2017

A highly reliable lightweight PUF circuit with temperature and voltage compensated for secure chip identification.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Design of ternary pulsed reversible counter based on CNFET.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Operating load based real-time rolling grey forecasting for machine health prognosis in dynamic maintenance schedule.
J. Intell. Manuf., 2015

Design of power-up and arbiter hybrid physical unclonable functions in 65nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electron. Express, 2014

Design of threshold dominant delay Physical Unclonable Functions in 65nm CMOS.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Highly stable data SRAM-PUF in 65nm CMOS process.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Design of a high information-density multiple valued 2-read 1-write register file.
IEICE Electron. Express, 2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.
IEICE Electron. Express, 2012

2011
Design of resistant DPA three-valued counter based on SABL.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2008
An Implementation of the Agency Architecture in Educational Robotics.
Proceedings of the 8th IEEE International Conference on Advanced Learning Technologies, 2008

2007
Pedagogical Agents for Teacher Intervention in Educational Robotics Classes: Implementation Issues.
Proceedings of the DIGITEL 2007, 2007

2006
Implementation of Intelligent Agents with Mobility in Educational Robotics Settings.
Proceedings of the 4th IEEE International Workshop on Wireless and Mobile Technologies in Education, 2006

Using Agents for Enhancing Learning Effects in an Advanced Discussion Forum.
Proceedings of the Learning by Effective Utilization of Technologies: Facilitating Intercultural Understanding, 2006

Agency Architecture for Teacher Intervention in Robotics Classes.
Proceedings of the 6th IEEE International Conference on Advanced Learning Technologies, 2006

2005
An Open-ended Framework for Learning Object Metadata Interchange.
Proceedings of the Towards Sustainable and Scalable Educational Innovations Informed by the Learning Sciences, 2005


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