Tianming Ni

Orcid: 0000-0001-6272-8660

According to our database1, Tianming Ni authored at least 78 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Reliability analysis and comparison of ring-PUF based on probabilistic models.
Microelectron. J., February, 2024

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

2023
Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix.
IEEE Trans. Aerosp. Electron. Syst., December, 2023

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications.
IEEE Des. Test, August, 2023

Worst-case Power Integrity Prediction Using Convolutional Neural Network.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments.
IEEE Trans. Aerosp. Electron. Syst., June, 2023

A Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch.
IEEE Trans. Aerosp. Electron. Syst., June, 2023

A Flexible and High-Performance Lattice-Based Post-Quantum Crypto Secure Coprocessor.
IEEE Trans. Ind. Informatics, 2023

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications.
IEEE Trans. Emerg. Top. Comput., 2023

Fault-avoidance C-element based low overhead and TNU-resilient latch.
Microelectron. J., 2023

A Low Overhead and Double-Node-Upset Self-Recoverable Latch.
Proceedings of the IEEE International Test Conference in Asia, 2023

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications.
Proceedings of the IEEE International Test Conference in Asia, 2023

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery.
Proceedings of the 10th International Conference on Dependable Systems and Their Applications, 2023

SASL-JTAG: A Light-Weight Dependable JTAG.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022
Calibration of SQUID Magnetometers in Multichannel MCG System Based on Bi-Planar Coil.
IEEE Trans. Instrum. Meas., 2022

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments.
IEEE Trans. Emerg. Top. Comput., 2022

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.
Integr., 2022

Valid test pattern identification for VLSI adaptive test.
Integr., 2022

Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement.
IEEE Des. Test, 2022

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS.
Proceedings of the IEEE International Test Conference in Asia, 2022

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Lightweight M_TRNG Design based on MUX Cell Entropy using Multiphase Sampling.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021
A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology.
IEEE Trans. Emerg. Top. Comput., 2021

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications.
Microelectron. J., 2021

A high-speed and triple-node-upset recovery latch with heterogeneous interconnection.
Microelectron. J., 2021

LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS.
Microelectron. J., 2021

Design of MNU-Resilient latches based on input-split C-elements.
Microelectron. J., 2021

Design of node separated triple-node-upset self-recoverable latch.
Microelectron. J., 2021

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier.
J. Circuits Syst. Comput., 2021

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs.
IEICE Electron. Express, 2021

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications.
J. Electron. Test., 2021

A Test Method for Large-size TSV Considering Resistive Open Fault and Leakage Fault Coexistence.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing.
Proceedings of the IEEE International Test Conference in Asia, 2021

A N: 1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs.
Proceedings of the IEEE International Test Conference in Asia, 2021

Kelvin Bridge Structure Based TSV Test for Weak Faults.
Proceedings of the IEEE International Test Conference in Asia, 2021

Continuous-time Delta-Sigma Modulators: Single-loop versus MASH.
Proceedings of the 18th International SoC Design Conference, 2021

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Architecture of Cobweb-Based Redundant TSV for Clustered Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets.
IEEE Trans. Circuits Syst., 2020

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC.
IEEE Trans. Circuits Syst., 2020

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment.
IEEE Trans. Computers, 2020

CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs.
J. Circuits Syst. Comput., 2020

A low critical path delay structure for composite field AES S-box based on constant matrices multiplication merging.
IEICE Electron. Express, 2020

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm.
IEEE Access, 2020

A SEU Immune Flip-Flop with Low Overhead.
Proceedings of the Machine Learning for Cyber Security - Third International Conference, 2020

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors.
Proceedings of the IEEE International Test Conference in Asia, 2020

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

An enhanced time-to-digital conversion solution for pre-bond TSV dual faults testing.
IEICE Electron. Express, 2019

Temperature-Aware Floorplanning for Fixed-Outline 3D ICs.
IEEE Access, 2019

A Novel Built-In Self-Repair Scheme for 3D Memory.
IEEE Access, 2019

Design of a Novel Self-Recoverable SRAM Cell Protected Against Soft Errors.
Proceedings of the 6th International Conference on Dependable Systems and Their Applications, 2019

2018
Research on physical unclonable functions circuit based on three dimensional integrated circuit.
IEICE Electron. Express, 2018

A novel in-field TSV repair method for latent faults.
IEICE Electron. Express, 2018

An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
A Region-Based Through-Silicon via Repair Method for Clustered Faults.
IEICE Trans. Electron., 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.
IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.
IEICE Electron. Express, 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.
IEICE Electron. Express, 2017

2016
NBTI mitigation by M-IVC with input duty cycle and randomness constraints.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016


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