Jian Luan

According to our database, Jian Luan authored at least 7 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2021

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS.

Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu

Proceedings of the 47th ESSCIRC 2021, 2021

A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency.

Jian Luan, Danyu Wu, Xuqiang Zheng, Chen Cai, Linzhen Wu, Lei Zhou, Jin Wu, Xinyu Liu

Proceedings of the 47th ESSCIRC 2021, 2021

2019

An 8 GSps 14 bit RF DAC With IM3<-62 dBc up to 3.6 GHz.

Dong Wang, Lei Zhou, DanYu Wu, Chonghe Ma, Jinxin Xue, Xuan Guo, Jian Luan, Huasen Liu, Jin Wu, Xinyu Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm.

Huasen Liu, DanYu Wu, Lei Zhou, Jian Luan, Xuan Guo, Dong Wang, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2019

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS.

Huasen Liu, DanYu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2019

A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer.

DanYu Wu, Lei Zhou, Huasen Liu, Yinkun Huang, Jian Luan, Xuan Guo, Jin Wu, Xinyu Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration.

Xiaoge Zhu, DanYu Wu, Lei Zhou, Chonghe Ma, Dandan Wang, Jian Luan, Yinkun Huang, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2017