Jian Luan

Affiliations:
  • Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China


According to our database1, Jian Luan authored at least 7 papers between 2017 and 2021.

Collaborative distances:

Timeline

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Bibliography

2021
A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021

A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency.
Proceedings of the 47th ESSCIRC 2021, 2021

2019
An 8 GSps 14 bit RF DAC With IM3<-62 dBc up to 3.6 GHz.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm.
IEICE Electron. Express, 2019

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS.
IEICE Electron. Express, 2019

A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017
A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration.
IEICE Electron. Express, 2017


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