Xuqiang Zheng
Orcid: 0000-0002-8978-6825
According to our database1,
Xuqiang Zheng
authored at least 41 papers
between 2012 and 2024.
Collaborative distances:
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Bibliography
2024
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
2023
Microelectron. J., October, 2023
2022
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
Microelectron. J., 2022
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.
IEEE Access, 2022
2021
A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds.
IEEE Trans. Neural Networks Learn. Syst., 2020
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
A CRNN System for Sound Event Detection Based on Gastrointestinal Sound Dataset Collected by Wearable Auscultation Devices.
IEEE Access, 2020
2019
IEICE Electron. Express, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
Design of high-speed SerDes transceiver for chip-to-chip communications in CMOS process.
PhD thesis, 2018
Microelectron. J., 2018
2017
IEEE J. Solid State Circuits, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A battery-less, 255 nA quiescent current temperature sensor with voltage regulator fully powered by harvesting ambient vibrational energy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A current-to-voltage integrator using area-efficient correlated double sampling technique.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012