Jiang Hu

According to our database1, Jiang Hu authored at least 200 papers between 1999 and 2018.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2016, "For contributions to gate, interconnect, and clock network optimization in VLSI circuits".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A Simple Yet Efficient Accuracy-Configurable Adder Design.
IEEE Trans. VLSI Syst., 2018

The Cat and Mouse in Split Manufacturing.
IEEE Trans. VLSI Syst., 2018

A Built-In Self-Test and In Situ Analog Circuit Optimization Platform.
IEEE Trans. on Circuits and Systems, 2018

Multi-scale performance simulation and effect analysis for hydraulic concrete submitted to leaching and frost.
Eng. Comput. (Lond.), 2018

NextSV: a meta-caller for structural variants from low-coverage long-read sequencing data.
BMC Bioinformatics, 2018

Simultaneous Wireless Information and Power Transfer in Cellular Two-Way Relay Networks With Massive MIMO.
IEEE Access, 2018

Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems.
Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018

Interconnect Optimization Considering Multiple Critical Paths.
Proceedings of the 2018 International Symposium on Physical Design, 2018

DUCER: a Fast and Lightweight Error Correction Scheme for In-Vehicle Network Communication.
Proceedings of the 2018 IEEE International Conference on Vehicular Electronics and Safety, 2018

Towards provably-secure analog and mixed-signal locking against overproduction.
Proceedings of the International Conference on Computer-Aided Design, 2018

Using imprecise computing for improved non-preemptive real-time scheduling.
Proceedings of the 55th Annual Design Automation Conference, 2018

Experience on Consumer Purchasing Decision-making: a Study of Anchoring Effects.
Proceedings of the 24th Americas Conference on Information Systems, 2018

Analyze the Factors of Firms to Rely on Internal and External Suppliers.
Proceedings of the 24th Americas Conference on Information Systems, 2018

Exploring Serverless Computing for Neural Network Training.
Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018

2017
A comparative study on neural network-based prediction of smart community energy consumption.
Proceedings of the 2017 IEEE SmartWorld, 2017

Thwarting analog IC piracy via combinational locking.
Proceedings of the IEEE International Test Conference, 2017

A Reliable Soil Moisture Sensing Methodology for Agricultural Irrigation.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Reinforcement Learning Control for Water-Efficient Agricultural Irrigation.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

A simple yet efficient accuracy configurable adder design.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Enhancing Datacenter Resource Management through Temporal Logic Constraints.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Front-end-of-line attacks in split manufacturing.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Making split fabrication synergistically secure and manufacturable.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Making split fabrication synergistically secure and manufacturable.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits.
Proceedings of the 54th Annual Design Automation Conference, 2017

A quantifiable approach to approximate computing: special session.
Proceedings of the 2017 International Conference on Compilers, 2017

Fast and Highly Scalable Bayesian MDP on a GPU Platform.
Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

Routing perturbation for enhanced security in split manufacturing.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Polynomial Regression and Measurement Error: Implications for IS Research.
Proceedings of the 23rd Americas Conference on Information Systems, 2017

2016
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory.
ACM Trans. Design Autom. Electr. Syst., 2016

Dam structural behavior identification and prediction by using variable dimension fractal model and iterated function system.
Appl. Soft Comput., 2016

Proximity Optimization for Adaptive Circuit Design.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Control synthesis and delay sensor deployment for efficient ASV designs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

The cat and mouse in split manufacturing.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Optimal design of JPEG hardware under the approximate computing paradigm.
Proceedings of the 53rd Annual Design Automation Conference, 2016

GPU acceleration for Bayesian control of Markovian genetic regulatory networks.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015
Proximity Sensing Based on a Dynamic Vision Sensor for Mobile Devices.
IEEE Trans. Industrial Electronics, 2015

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Built-In Self Optimization for Variation Resilience of Analog Filters.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A pre-search assisted ILP approach to analog integrated circuit routing.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

GPU acceleration for PCA-based statistical static timing analysis.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Timing verification for adaptive integrated circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Joint precision optimization and high level synthesis for approximate computing.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Regularity-constrained floorplanning for multi-core processors.
Integration, 2014

STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Algorithms for power-efficient QoS in application specific NoCs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Dual-Level Adaptive Supply Voltage System for Variation Resilience.
IEEE Trans. VLSI Syst., 2013

Boostable Repeater Design for Variation Resilience in VLSI Interconnects.
IEEE Trans. VLSI Syst., 2013

In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches.
ACM Trans. Design Autom. Electr. Syst., 2013

Guest editorial: Special section on cross-domain physical optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Multifractal scaling behavior analysis for existing dams.
Expert Syst. Appl., 2013

Resource allocation algorithms for guaranteed service in application-specific NoCs.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Power gating with block migration in chip-multiprocessor last-level caches.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Dynamic voltage and frequency scaling for shared resources in multicore processor designs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Guest Editorial Special Section on the 2011 International Symposium on Physical Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

A node scheduling based on partition for WSN.
Proceedings of the 2012 Wireless Telecommunications Symposium, 2012

In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Track assignment considering crosstalk-induced performance degradation.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies.
VLSI Design, 2011

GPU-Based Parallelization for Fast Circuit Optimization.
ACM Trans. Design Autom. Electr. Syst., 2011

Simultaneous Technology Mapping and Placement for Delay Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

A mean shift based small target tracking algorithm in colored video.
Proceedings of the Third International Conference of Soft Computing and Pattern Recognition, 2011

Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Lagrangian relaxation for gate implementation selection.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Regularity-constrained floorplanning for multi-core processors.
Proceedings of the 2011 International Symposium on Physical Design, 2011

A bilinear interpolation mean shift small target tracking algorithm.
Proceedings of the 5th International Conference on Signal Processing and Communication Systems, 2011

Gate sizing and device technology selection algorithms for high-performance industrial designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Combinatorial Algorithms for Fast Clock Mesh Optimization.
IEEE Trans. VLSI Syst., 2010

An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.
IEEE Trans. VLSI Syst., 2010

Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks.
IEEE Trans. VLSI Syst., 2010

Pattern Sensitive Placement Perturbation for Manufacturability.
IEEE Trans. VLSI Syst., 2010

Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

A dual-level adaptive supply voltage system for variation resilience.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Useful clock skew optimization under a multi-corner multi-mode design framework.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Accurate clock mesh sizing via sequential quadraticprogramming.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Clustering-based simultaneous task and voltage scheduling for NoC systems.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal.
Proceedings of the Design, Automation and Test in Europe, 2010

Detecting tangled logic structures in VLSI netlists.
Proceedings of the 47th Design Automation Conference, 2010

Physical design techniques for optimizing RTA-induced variations.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Clock Buffer Polarity Assignment for Power Noise Reduction.
IEEE Trans. VLSI Syst., 2009

Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations.
IEEE Trans. VLSI Syst., 2009

Gate Sizing for Cell-Library-Based Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

A fast general slew constrained minimum cost buffering algorithm.
Microelectronics Journal, 2009

A single layer zero skew clock routing in X architecture.
Science in China Series F: Information Sciences, 2009

A new algorithm for simultaneous gate sizing and threshold voltage assignment.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Impact of lithography-friendly circuit layout.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

GPU-based parallelization for fast circuit optimization.
Proceedings of the 46th Design Automation Conference, 2009

2008
Buffering in the Layout Environment.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Timing-Driven Interconnect Synthesis.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Buffer Insertion Basics.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Power Grid Analysis and Optimization Using Algebraic Multigrid.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Robust Clock Tree Routing in the Presence of Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Buffering Interconnect for Multicore Processor Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.
Integration, 2008

ASIC design flow considering lithography-induced effects.
IET Circuits, Devices & Systems, 2008

Low Power Gated Clock Tree Driven Placement.
IEICE Transactions, 2008

Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Elastic Timing Scheme for Energy-Efficient and Robust Performance.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Activity and register placement aware gated clock network design.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Discrete buffer and wire sizing for link-based non-tree clock networks.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Multi-scenario buffer insertion in multi-core processor designs.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Gate planning during placement for gated clock network.
Proceedings of the 26th International Conference on Computer Design, 2008

Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Built-In Proactive Tuning System for Circuit Aging Resilience.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Handling partial correlations in yield prediction.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Integrated Placement and Skew Optimization for Rotary Clocking.
IEEE Trans. VLSI Syst., 2007

Utilizing Redundancy for Timing Critical Interconnect.
IEEE Trans. VLSI Syst., 2007

Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.
IEEE Trans. VLSI Syst., 2007

Path-Based Buffer Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Placement Methodology for Robust Clocking.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

An Efficient Algorithm for RLC Buffer Insertion.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Pattern sensitive placement for manufacturability.
Proceedings of the 2007 International Symposium on Physical Design, 2007

The influence of user tailoring and cognitive load on user performance in spoken dialogue systems.
Proceedings of the INTERSPEECH 2007, 2007

Modeling, optimization and control of rotary traveling-wave oscillator.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Unified adaptivity optimization of clock and logic signals.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Gate Sizing For Cell Library-Based Designs.
Proceedings of the 44th Design Automation Conference, 2007

Context & usability testing: user-modeled information presentation in easy and difficult driving conditions.
Proceedings of the 2007 Conference on Human Factors in Computing Systems, 2007

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Antenna Avoidance in Layer Assignment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Analytical bound for unwanted clock skew due to wire width variation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Reducing clock skew variability via crosslinks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Accurate estimation of global buffer delay within a floorplan.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Low Power Trellis Decoder with Overscaled Supply Voltage.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

An Improved AMG-based Method for Fast Power Grid Analysis.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Efficient Model Update for General Link-Insertion Networks.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Statistical clock tree routing for robustness to process variations.
Proceedings of the 2006 International Symposium on Physical Design, 2006

High performance clock routing in X-architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Fast decap allocation based on algebraic multigrid.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Combinatorial algorithms for fast clock mesh optimization.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Clock buffer polarity assignment for power noise reduction.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A new RLC buffer insertion algorithm.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Integrated placement and skew optimization for rotary clocking.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Associative skew clock routing for difficult instances.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Steiner network construction for timing critical nets.
Proceedings of the 43rd Design Automation Conference, 2006

Fast algorithms for slew constrained minimum cost buffering.
Proceedings of the 43rd Design Automation Conference, 2006

Standard cell characterization considering lithography induced variations.
Proceedings of the 43rd Design Automation Conference, 2006

Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice.
Proceedings of the 2006 Conference on Human Factors in Computing Systems, 2006

groupTime: preference based group scheduling.
Proceedings of the 2006 Conference on Human Factors in Computing Systems, 2006

2005
An efficient merging scheme for prescribed skew clock routing.
IEEE Trans. VLSI Syst., 2005

Navigating Register Placement for Low Power Clock Network Design.
IEICE Transactions, 2005

Natural Language Interface Put in Perspective: Interaction of Search Method and Task Complexity.
Proceedings of the Natural Language Understanding and Cognitive Science, 2005

Coupling aware timing optimization and antenna avoidance in layer assignment.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Improved algorithms for link-based non-tree clock networks for skew variability reduction.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences.
Proceedings of the Human-Computer Interaction, 2005

Preference-Based Group Scheduling.
Proceedings of the Human-Computer Interaction, 2005

DiCER: distributed and cost-effective redundancy for variation tolerance.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Practical techniques to reduce skew and its variations in buffered clock networks.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Path based buffer insertion.
Proceedings of the 42nd Design Automation Conference, 2005

Navigating registers in placement for clock network minimization.
Proceedings of the 42nd Design Automation Conference, 2005

Timing driven track routing considering coupling capacitance.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Skew scheduling and clock routing for improved tolerance to process variations.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Register placement for low power clock network.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Making fast buffer insertion even faster via approximation techniques.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Clock network minimization methodology based on incremental placement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Library cell layout with Alt-PSM compliance and composability.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A methodology for the simultaneous design of supply and signal networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Porosity-aware buffered Steiner tree construction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Buffered Clock Tree for High Quality IC Design.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Exploiting level sensitive latches in wire pipelining.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Accurate estimation of global buffer delay within a floorplan.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Reducing clock skew variability via cross links.
Proceedings of the 41th Design Automation Conference, 2004

Fast and flexible buffer trees that navigate the physical layout environment.
Proceedings of the 41th Design Automation Conference, 2004

Layer assignment for crosstalk risk minimization.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A place and route aware buffered Steiner tree construction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Buffer insertion with adaptive blockage avoidance.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

A practical methodology for early buffer and wire resource allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Process variation aware clock tree routing.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Porosity aware buffered steiner tree construction.
Proceedings of the 2003 International Symposium on Physical Design, 2003

A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Analytical Bound for Unwanted Clock Skew due to Wire Width Variation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Performance Driven Global Routing Through Gradual Refinement.
VLSI Design, 2002

A timing-constrained simultaneous global routing algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Buffer insertion with adaptive blockage avoidance.
Proceedings of 2002 International Symposium on Physical Design, 2002

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
Proceedings of 2002 International Symposium on Physical Design, 2002

Congestion-driven codesign of power and signal networks.
Proceedings of the 39th Design Automation Conference, 2002

2001
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

A survey on multi-net global routing for integrated circuits.
Integration, 2001

Buffered Steiner trees for difficult instances.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Steiner tree optimization for buffers. Blockages and bays.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Performance Driven Global Routing Through Gradual Refinement.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A Practical Methodology for Early Buffer and Wire Resource Allocation.
Proceedings of the 38th Design Automation Conference, 2001

2000
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Non-Hanan routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model.
Proceedings of the 1999 International Symposium on Physical Design, 1999

FAR-DS: Full-Plane AWE Routing with Driver Sizing.
Proceedings of the 36th Conference on Design Automation, 1999


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