Rupesh S. Shelar

According to our database, Rupesh S. Shelar authored at least 20 papers between 1999 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops.

Rupesh S. Shelar

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2013

Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor.

Rupesh S. Shelar, Marek Patyra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012

A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis.

Rupesh S. Shelar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

Simultaneous Technology Mapping and Placement for Delay Minimization.

Yifang Liu, Rupesh S. Shelar, Jiang Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Routing With Constraints for Post-Grid Clock Distribution in Microprocessors.

Rupesh S. Shelar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.

Rupesh S. Shelar

Proceedings of the 2009 International Symposium on Physical Design, 2009

2008

Estimation of Routing Congestion.

Rupesh S. Shelar, Prashant Saxena

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.

Yifang Liu, Rupesh S. Shelar, Jiang Hu

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

An efficent clustering algorithm for low power clock tree synthesis.

Rupesh S. Shelar

Proceedings of the 2007 International Symposium on Physical Design, 2007

Routing Congestion in VLSI Circuits - Estimation and Optimization.

Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar

Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-48550-8, 2007

2006

Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints.

Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005

BDD decomposition for delay oriented pass transistor logic synthesis.

Rupesh S. Shelar, Sachin S. Sapatnekar

IEEE Trans. Very Large Scale Integr. Syst., 2005

A predictive distributed congestion metric with application to technology mapping.

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

An efficient technology mapping algorithm targeting routing congestion under delay constraints.

Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar

Proceedings of the 2005 International Symposium on Physical Design, 2005

2004

A predictive distributed congestion metric and its application to technology mapping.

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang

Proceedings of the 2004 International Symposium on Physical Design, 2004

2002

An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis.

Rupesh S. Shelar, Sachin S. Sapatnekar

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits.

Rupesh S. Shelar, Sachin S. Sapatnekar

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001

Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits.

Rupesh S. Shelar, Sachin S. Sapatnekar

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

Parameterized Reusable Component Library Methodology.

Rupesh S. Shelar, Sacheendra Nath, Jagmohan S. Nanaware

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999

Decomposition of Finite State Machines for Area, Delay Minimization.

Rupesh S. Shelar, Madhav P. Desai, H. Narayanan

Proceedings of the IEEE International Conference On Computer Design, 1999