Patrick H. Madden

According to our database1, Patrick H. Madden authored at least 42 papers between 1993 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

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Bibliography

2013
Dispelling the Myths of Parallel Computing.
IEEE Design & Test, 2013

"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

2012
Filtering of MS/MS data for peptide identification.
Proceedings of the IEEE 2nd International Conference on Computational Advances in Bio and Medical Sciences, 2012

2011
Poster: De novo protein identification by dynamic programming.
Proceedings of the IEEE 1st International Conference on Computational Advances in Bio and Medical Sciences, 2011

Mathematical limits of parallel computation for embedded systems.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Customized architectures for faster route finding in GPS-based navigation systems.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

A co-processor approach for accelerating data-structure intensive algorithms.
Proceedings of the 28th International Conference on Computer Design, 2010

An effective approach for large scale floorplanning.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2008
Legalization and Detailed Placement.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

2007
Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

ISPD placement contest updates and ISPD 2007 global routing contest.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Bisection Based Placement for the X Architecture.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Analytic Placement using Minimum Cost Flow.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005
Mixed block placement via fractional cut recursive bisection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Recursive bisection placement: feng shui 5.0 implementation details.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Performance analysis by topology indexed lookup tables.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Optimal placement by branch-and-price.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

On structure and suboptimality in placement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Floorplan management: incremental placement for gate sizing and buffer insertion.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Recursive bisection based mixed block placement.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Routability-driven placement and white space allocation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
Benchmarking for large-scale placement and beyond.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Fractional Cut: Improved Recursive Bisection Placement.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Congestion reduction in traditional and new routing architectures.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Crosstalk Reduction in Area Routing.
Proceedings of the 2003 Design, 2003

Improved global routing through congestion estimation.
Proceedings of the 40th Design Automation Conference, 2003

2001
Interconnect layout optimization under higher order RLC model forMCM designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Reporting of standard cell placement results.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Global objectives for standard cell placement.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Preferred direction Steiner trees.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Improved Cut Sequences for Partitioning Based Placement.
Proceedings of the 38th Design Automation Conference, 2001

Parallel Standard Cell Placement on a Cluster of Workstations.
Proceedings of the 2001 IEEE International Conference on Cluster Computing (CLUSTER 2001), 2001

2000
InfoFlo: a novel communication infrastructure for personal digital assistants.
Proceedings of the IEEE International Conference on Systems, 2000

Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
Partitioning by iterative deletion.
Proceedings of the 1999 International Symposium on Physical Design, 1999

1998
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Performance-driven routing with multiple sources.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Performance driven global routing for standard cell design.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1996
Performance optimization of VLSI interconnect layout.
Integration, 1996

1995
Performance Driven Routing with Mulitiple Sources.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1993
Multiple fault testing using minimal single fault test set for fanout-free circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993


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