Jiangmin Gu

According to our database, Jiangmin Gu authored at least 13 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

The Investigation of Source Field Plate on the Performance of pGaN Gate Device and Dual-Gate Bidirectional Switch using TCAD Simulation.

Xuan Chi, Yubo Wang, Fan Li, Yixiao Huang, Chenruiyuan Yu, Shiqiang Wu, Huiqing Wen, Jiangmin Gu, Ping Zhang, Wen Liu

Proceedings of the International Conference on IC Design and Technology, 2023

2011

A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process.

Jinna Yan, Kok Meng Lim, Jiangmin Gu, Keping Wang, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo

Proceedings of the International SoC Design Conference, 2011

SiGe BiCMOS power amplifiers for 60GHz ISM band applications.

Renjing Pan, Jiangmin Gu, Kiat Seng Yeo, Wei Meng Lim, Kaixue Ma

Proceedings of the International SoC Design Conference, 2011

Ultra low power active 60 GHz Bi-CMOS down-conversion mixer.

Kok Meng Lim, Jiangmin Gu, Jinna Yan, Wei Meng Lim, Yang Lu, Kiat Seng Yeo

Proceedings of the International SoC Design Conference, 2011

2010

Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving power.

Kok Meng Lim, Jiangmin Gu, Yang Lu, Jinna Yan, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2005

A review of 0.18-μm full adder performances for tree structured arithmetic circuits.

Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang

IEEE Trans. Very Large Scale Integr. Syst., 2005

A novel covalent redundant binary Booth encoder.

Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An area efficient 64-bit square root carry-select adder for low power applications.

Yajuan He, Chip-Hong Chang, Jiangmin Gu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits.

Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

2003

A novel hybrid pass logic with static CMOS output drive full-adder cell.

Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Ultra low voltage, low power 4-2 compressor for high speed multiplications.

Jiangmin Gu, Chip-Hong Chang

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low voltage, low power (5: 2) compressor cell for fast arithmetic circuits.

Jiangmin Gu, Chip-Hong Chang

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002

An interconnect optimized floorplanning of a scalar product macrocell.

Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002