Jiansong Wan

According to our database, Jiansong Wan authored at least 11 papers between 2011 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

FIRE: A Comprehensive Benchmark for Financial Intelligence and Reasoning Evaluation.

Xiyuan Zhang, Huihang Wu, Jiayu Guo, Zhenlin Zhang, Yiwei Zhang, Liangyu Huo, Xiaoxiao Ma, Jiansong Wan, Xuewei Jiao, Yi Jing, Jian Xie

CoRR, February, 2026

2025

PIG-Nav: Key Insights for Pretrained Image Goal Navigation Models.

Jiansong Wan, Chengming Zhou, Jinkua Liu, Xiangge Huang, Xiaoyu Chen, Xiaohan Yi, Qisen Yang, Baiting Zhu, Xin-Qiang Cai, Lixing Liu, Rushuai Yang, Chuheng Zhang, Sherif Abdelfattah, Hayong Shin, Pushi Zhang, Li Zhao, Jiang Bian

CoRR, July, 2025

2024

A novel semi-supervised model for pre-impact fall detection with limited fall data.

Xiaoqun Yu, Jiansong Wan, Guoyuan An, Xu Yin, Shuping Xiong

Eng. Appl. Artif. Intell., 2024

Traffic pattern-aware elevator dispatching via deep reinforcement learning.

Jiansong Wan, Kanghoon Lee, Hayong Shin

Adv. Eng. Informatics, 2024

2022

Predictive vehicle dispatching method for overhead hoist transport systems in semiconductor fabs.

Jiansong Wan, Hayong Shin

Int. J. Prod. Res., 2022

Hierarchical analysis of Chinese financial market based on manifold structure.

Yan Huang, Jiansong Wan

Ann. Oper. Res., 2022

2015

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.

Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS.

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers.

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2011

An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS.

Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult

IEEE J. Solid State Circuits, 2011

An 800MS/s dual-residue pipeline ADC in 40nm CMOS.

Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult

Proceedings of the IEEE International Solid-State Circuits Conference, 2011