Jan Mulder

According to our database, Jan Mulder authored at least 24 papers between 1997 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Session 16 overview: Gigahertz data converters.

Jan Mulder, Paul Ferguson, Un-Ku Moon

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference.

Edgar Sánchez-Sinencio, Jan Mulder, Antonio Liscidini, Eric A. M. Klumperink, Elad Alon

IEEE J. Solid State Circuits, 2016

2015

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.

Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS.

Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult

IEEE J. Solid State Circuits, 2014

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS.

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS.

Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers.

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2011

An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS.

Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult

IEEE J. Solid State Circuits, 2011

An 800MS/s dual-residue pipeline ADC in 40nm CMOS.

Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A Low-Power Capacitive Charge Pump Based Pipelined ADC.

Imran Ahmed, Jan Mulder, David A. Johns

IEEE J. Solid State Circuits, 2010

2009

A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS.

Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult

IEEE J. Solid State Circuits, 2009

A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS.

Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps.

Imran Ahmed, Jan Mulder, David A. Johns

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2005

The e-Xperimenteren+ Project: Pool of Remote Experiments and Software Environment.

Jasper Bedaux, Leendert Van Gastel, Piet Blankert, Jan Mulder, Jeroen Verschuur, Wopke Wijngaard

Int. J. Online Eng., 2005

2004

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm² 0.13-μm CMOS.

Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes

IEEE J. Solid State Circuits, 2004

2001

Advances in low-voltage ultra-low-power analog circuit design.

Wouter A. Serdijn, Jan Mulder, Daniel Rocha, Luís Cléber C. Marques

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999

A low-voltage translinear second-order quadrature oscillator.

Wouter A. Serdijn, Jan Mulder, Michiel H. L. Kouwenhoven, Arthur H. M. van Roermund

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Analysis of noise in higher-order translinear filters.

Michiel H. L. Kouwenhoven, Jan Mulder, Wouter A. Serdijn, Arthur H. M. van Roermund

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

A wide-tunable translinear second-order oscillator.

Wouter A. Serdijn, Jan Mulder, Albert C. van der Woerd, Arthur H. M. van Roermund

IEEE J. Solid State Circuits, 1998

An ultra-low-power, low-voltage electronic audio delay line for use in hearing aids.

L. P. L. van Dijk, Albert C. van der Woerd, Jan Mulder, Arthur H. M. van Roermund

IEEE J. Solid State Circuits, 1998

A new current mode synthesis method for dynamic translinear filters and its application in hearing aids.

Dorra Masmoudi, Wouter A. Serdijn, Jan Mulder, Albert C. van der Woerd, Jean Tomas, Jean Paul Dom

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997

A low-voltage ultra-low-power translinear integrator for audio filter applications.

Wouter A. Serdijn, Martijn Broest, Jan Mulder, Albert C. van der Woerd, Arthur H. M. van Roermund

IEEE J. Solid State Circuits, 1997

An RMS-DC converter based on the dynamic translinear principle.

Jan Mulder, Albert C. van der Woerd, Wouter A. Serdijn, Arthur H. M. van Roermund

IEEE J. Solid State Circuits, 1997

A reduced-area low-power low-voltage single-ended differential pair.

Jan Mulder, Marcel van de Gevel, Arthur H. M. van Roermund

IEEE J. Solid State Circuits, 1997