Klaas Bult

According to our database, Klaas Bult authored at least 24 papers between 1997 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers.

Md Shakil Akter, Rohan Sehgal, Klaas Bult

IEEE Trans. Circuits Syst., 2020

2018

A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers.

Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult

IEEE J. Solid State Circuits, 2018

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier.

Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Kofi A. A. Makinwa, Klaas Bult

IEEE J. Solid State Circuits, 2018

A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier.

Md Shakil Akter, Kofi A. A. Makinwa, Klaas Bult

IEEE J. Solid State Circuits, 2018

2017

A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers.

Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2015

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration.

Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult

IEEE J. Solid State Circuits, 2015

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.

Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction.

Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult

Proceedings of the ESSCIRC Conference 2015, 2015

2014

A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS.

Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult

IEEE J. Solid State Circuits, 2014

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS.

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS.

Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration.

Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult

Proceedings of the ESSCIRC 2014, 2014

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers.

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS.

Silvian Spiridon, Johan van der Tang, Han Yan, Hua-feng Chen, Davide Guermandi, Xiaodong Liu, Erol Arslan, Frank M. L. van der Goes, Klaas Bult

IEEE J. Solid State Circuits, 2013

2011

An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS.

Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult

IEEE J. Solid State Circuits, 2011

An 800MS/s dual-residue pipeline ADC in 40nm CMOS.

Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS.

Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult

IEEE J. Solid State Circuits, 2009

A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS.

Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Embedded analog-to-digital converters.

Klaas Bult

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2004

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm² 0.13-μm CMOS.

Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes

IEEE J. Solid State Circuits, 2004

1999

A single-chip universal digital satellite receiver with 480-MHz IF input.

Alan Y. Kwentus, Patrick Pai, Steven Jaffe, Ray Gomez, Shauhyuarn Sean Tsai, Tom Kwan, Hing T. Hung, Young J. Shin, Vin Hue, Darwin Cheung, Raheel A. Khan, Christopher M. Ward, Mong-Kai Ku, Kenneth Choi, Jim Searle, Klaas Bult, Kelly B. Cameron, Jason Demas, Charles Reames, Henry Samueli

IEEE J. Solid State Circuits, 1999

1998

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm².

Chi-Hung Lin, Klaas Bult

IEEE J. Solid State Circuits, 1998

Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers.

Mehdi Hatamian, Oscar E. Agazzi, John Creigh, Henry Samueli, Andrew J. Castellano, David Kruse, Avi Madisetti, Nariman Yousefi, Klaas Bult, Patrick Pai, Myles Wakayama, Mike M. McConnell, Marty Colombatt

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm².

Klaas Bult, Aaron Buchwald

IEEE J. Solid State Circuits, 1997