Jiaping Tang

According to our database, Jiaping Tang authored at least 6 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Extend IVerilog to Support Batch RTL Fault Simulation.

Jiaping Tang, Jianan Mu, Zizhen Liu, Zhiteng Chao, Jing Ye, Huawei Li

CoRR, May, 2025

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy.

Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shenwen Liang, Jing Ye, Huawei Li, Xiaowei Li

CoRR, April, 2025

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy.

Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the Design, Automation & Test in Europe Conference, 2025

ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring.

Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism.

Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction.

Jiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye, Xiaowei Li, Huawei Li

Proceedings of the 33rd IEEE Asian Test Symposium, 2024