Jiaqi Yang

Orcid: 0009-0008-1195-8114

Affiliations:

Peking University, Institute for Artificial Intelligence, Beijing, China
Peking University, School of Integrated Circuits, Beijing, China
Southern University of Science and Technology, School of Microelectronics, Shenzhen, China

According to our database¹, Jiaqi Yang authored at least 5 papers between 2025 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2026

ESTroM: Element-Flow Architecture for Processing Sparse Tractable Probabilistic Models.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

M3DKV: Monolithic 3D Gain Cell Memory Enabled Efficient KV Cache & Processing.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025

A 20.98TOPS/W Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2025

A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

Jiaqi Yang

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