Jiawen Chen
Orcid: 0009-0002-0451-2401Affiliations:
- University College Dublin, School of Electrical and Electronic Engineering, Dublin, Ireland
- South China University of Technology, Laboratory of Millimeter-Wave and Terahertz, Guangzhou, China (former)
According to our database1,
Jiawen Chen authored at least 6 papers
between 2023 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
A 24.5-45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation.
IEEE J. Solid State Circuits, April, 2026
27.9 A Dual-Mode DCO-PA with a Twisted 8-Shape Inductor for BLE Achieving 42% TX Efficiency at 1.6dBm and 0.29mW RX Clock.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
A Compact Broadband Voltage-Combined Doherty Power Amplifier With Shorted Transmission Line for 5G Millimeter-Wave.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024
2023
A 24-to-30 GHz Series-Doherty Power Amplifier With Novel Broadband Combiner Achieving 2.5% Back-off PAE Variation in 65-nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023